View PM5346-RC_1533441.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ pmc-sierra, inc. 8501 commerce court burnaby, bc canada v5a 4n3 604 668 7300 pm5346 s/uni-155-lite saturn user network interface 155.52 & 51.84 mbit/s issue 6: march, 1996
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ i contents features ....................................................................................................................... 1 applications ............................................................................................................... 3 references ................................................................................................................. 3 application examples ........................................................................................... 4 block diagram............................................................................................................ 5 description ................................................................................................................. 6 pin diagram................................................................................................................... 8 pin description.......................................................................................................... 9 functional description....................................................................................... 20 clock recovery ....................................................................................................... 20 serial to parallel converter .................................................................................. 21 receive section overhead processor................................................................ 21 receive line overhead processor...................................................................... 23 receive path overhead processor ..................................................................... 24 receive atm cell processor ................................................................................ 25 clock synthesis ...................................................................................................... 29 parallel to serial converter .................................................................................. 29 transmit section overhead processor............................................................... 29 transmit line overhead processor..................................................................... 30 transmit path overhead processor .................................................................... 32 transmit atm cell processor ............................................................................... 34 drop side interface ................................................................................................ 36 microprocessor interface ....................................................................................... 37 register memory map ............................................................................................ 38 normal mode register description ............................................................. 40 test features description................................................................................ 99 test mode register memory map ........................................................................ 99 register 0x80: master test.............................................................................. 100
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ ii test mode 0 details................................................................................................ 101 operation...................................................................................................................... 102 overhead byte usage............................................................................................ 102 cell data structure ................................................................................................. 105 loopback operation............................................................................................... 106 driving differential inputs single ended ............................................................ 109 board design recommendations........................................................................ 109 interfacing to ecl or pecl devices ................................................................... 110 clock recovery ....................................................................................................... 111 clocking options..................................................................................................... 114 functional timing .................................................................................................... 117 drop side receive interface................................................................................. 117 drop side transmit interface................................................................................ 119 absolute maximum ratings ................................................................................ 121 d.c. characteristics.............................................................................................. 122 microprocessor interface timing characteristics ......................... 125 s/uni-lite timing characteristics .................................................................. 129 ordering and thermal information.............................................................. 138 mechanical information...................................................................................... 139 128 pin copper leadframe rectangular pqfp (r suffix): ............................. 139
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 1 features single chip atm user-network interface operating at 155.52 and 51.84 mbit/s. also capable of operating at atm forum mid-range phy subrates of 25.92 and 12.96 mbit/s. implements the atm forum user network interface specification and the atm physical layer for broadband isdn according to ccitt recommendation i.432. processes duplex 155.52 mbit/s sts-3c/stm-1 or 51.84 mbit/s sts-1 data streams with on-chip clock and data recovery and clock synthesis. provides saturn compliant interface - physical layer (sci-phy) fifo buffers in both transmit and receive paths with parity support. inserts and extracts the generic flow control (gfc) bits via a simple serial interface and provides a transmit xoff function to allow for local flow control. provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. low power, +5 volt, cmos technology. 128 pin high performance plastic quad flat pack (pqfp) 14 mm x 20 mm package. the receiver section: provides a serial interface at 155.52 or 51.84 mbit/s recovers the clock and data; frames to the recovered data stream; descrambles the received data; interprets the received payload pointer (h1, h2); and extracts the sts-3c or sts-1 synchronous payload envelope (vc4) and path overhead. extracts atm cells from the synchronous payload envelope using atm cell delineation and provides optional atm cell payload descrambling, header check sequence (hcs) error detection and error correction, and idle/unassigned cell filtering. provides a synchronous 8-bit wide, four cell fifo buffer. detects loss of signal (los), out of frame (oof), loss of frame (lof), line alarm indication signal (ais), line remote defect indication (rdi), loss of pointer (lop), path alarm indication signal (ais), loss of cell delineation and path rdi.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 2 counts received section bip-8 (b1) errors, received line bip-8/24 (b2) errors, line far end block errors (febe), received path bip-8 (b3) errors and path far end block errors (febe). counts received hcs errored cells that are discarded, received hcs errored cells that are corrected and passed on, and the total received cells passed on. the transmitter section: provides a synchronous 8-bit wide, four cell fifo buffer. provides idle/unassigned cell insertion, hcs generation/insertion, and atm cell payload scrambling; inserts atm cells into the transmitted sts-3c (stm-1) or sts-1 synchronous payload envelope using h4 framing generates the transmit payload pointer (h1, h2) and inserts the path overhead; scrambles the transmitted sts-3c (stm-1) or sts-1 stream and inserts framing bytes (a1, a2) and the identity byte (c1). synthesizes the 155.52 mhz, 51.84 mhz transmit clock from a one-eighth frequency reference. provides a serial interface at 155.52 or 51.84 mbit/s inserts path alarm indication signal (ais), path remote defect indication (rdi), line alarm indication signal (ais) and line rdi. inserts path bip-8 codes (b3), path far end block error (febe) indications, line bip-8/24 codes (b2), line far end block error (febe) indications, section bip-8 codes (b1) to allow performance monitoring at the far end. allows forced insertion of all zeros data (after scrambling) or corruption of framing byte or section, line, or path bip-8 codes for diagnostic purposes.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 3 applications workstations and personal computers switches and hubs routers sonet or sdh atm interfaces 155 and 51 mbit/s utp-5 atm lans 51, 25 and 13 mbit/s utp-3 atm lans references ccitt recommendation g.709 - "synchronous multiplexing structure", 1990. ccitt recommendation i.432 - "b-isdn user-network interface - physical interface specification", june 1990. bell communications research - sonet transport systems: common generic criteria, gr-253-core, issue 1, december 1994. atm forum - atm user-network interface specification,v3.0, september 10, 1993 t1.105, american national standard for telecommunications - digital hierarchy - optical interface rates and formats specifications (sonet), 1991 atm forum 155 mbit/s physical medium dependent (pmd) twisted pair copper specification draft (155-c5-utp-pmd, rev 0.2)
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 4 application examples the pm5346 s/uni-lite is typically used to implement the core of an atm user network interface by which an atm terminal is linked to an atm switching system using sonet/sdh compatible transport. the s/uni-lite finds application at either end of terminal to switch links or switch to switch links, both in private network (lan) and public network (wan) situations. in this application, the s/uni-lite typically interfaces on its line side with a line receiver/equalizer and a line driver. the s/uni-lite may be loop timed internally (the recovered clock is used in the transmit direction) or source timed (separate transmit and receive clocks). the drop side interfaces directly with atm adaptation layer or atm layer processors. the initial configuration and ongoing control and monitoring of the s/uni-lite is provided via a generic microprocessor interface. the s/uni-lite also supports a "hardware-only" operating mode where an external microprocessor is not required. this application is shown in figure?. fig. 1 typical atm adapter interface rxd+/- tfclk rdat[7:0] rsoc rfclk tdat[7:0] tsoc txd+/- atm terminal pm5346 s/uni-lite saturn user network interface rca tca twrenb rrdenb line driver & transformer transformer & line receiver receive aal processor transmit aal processor rxprty txprty
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 5 block diagram tx atm cell fifo rx atm cell fifo txd+ rrclk+ rxd+ ralm tdat[7:0 ] tca tsoc rdat[7:0 ] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfcl k trclk+ tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. alos+ driver data recovery clk rec. rbyp tbyp rxd- trclk- alos- rrclk- tclk tsen tgfc rcp tfpo txd- txc+ tcp rgfc txc- rxdo+ rxdo- rate0 rate1 atp2 atp1 txprty rxprt y xoff lf+ lf- lfo
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 6 description the pm5346 s/uni-lite saturn user network interface is a monolithic integrated circuit that implements the sonet/sdh processing and atm mapping functions of a 155 mbit/s or 51mbit/s atm user network interface. it is fully compliant with both sonet and sdh requirements and atm forum uni specifications. the s/uni-lite receives sonet/sdh frames via a bit serial interface, recovers clock and data, and processes section, line, and path overhead. it performs framing (a1, a2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (b1, b2, b3), accumulating error counts at each level for performance monitoring purposes. line and path far end block error indications (z2, g1) are also accumulated. the s/uni-lite interprets the received payload pointers (h1, h2) and extracts the synchronous payload envelope which carries the received atm cell payload. the s/uni-lite frames to the atm payload using cell delineation. hcs error correction is provided. idle/unassigned cells may be dropped according to a programmable filter. cells are also dropped upon detection of an uncorrectable header check sequence error. the atm cell payloads are descrambled. generic flow control (gfc) bits from error free cells are extracted and presented on a serial link for external processing. legitimate atm cells are written to a four cell fifo buffer. these cells are read from the fifo using a synchronous 8 bit wide datapath interface with cell-based handshake. counts of received atm cell headers that are errored and uncorrectable, those that are errored and correctable and all passed cells are accumulated independently for performance monitoring purposes. the s/uni-lite transmits sonet/sdh frames via a bit serial interface and formats section, line, and path overhead appropriately. it performs framing pattern insertion (a1, a2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (b1, b2, b3) as required to allow performance monitoring at the far end. line and path far end block error indications (z2, g1) are also inserted. the s/uni-lite generates the payload pointer (h1, h2) and inserts the synchronous payload envelope which carries the atm cell payload. it supports the insertion of a variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics. atm cells are written to an internal programmable-length 4-cell fifo using a synchronous 8 bit wide datapath interface. idle/unassigned cells are automatically inserted when the internal fifo contains less than one cell or the xoff input is asserted. generic flow control (gfc) bits may be inserted downstream of the fifo
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 7 via a serial link so that all fifo latency may be bypassed. a transmission off (xoff) input is provided to allow the suspension of active atm cell transmission independent of the fifo fill state. the s/uni-lite generates of the header check sequence and scrambles the payload of the atm cells. payload scrambling can be disabled. no line rate clocks are required directly by the s/uni-lite as it synthesizes the transmit clock and recovers the receive clock using a 19.44 mhz or 6.48 mhz reference clock. the s/uni-lite is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. it is implemented in low power, +5 volt cmos technology. it has ttl and pseudo ecl (pecl) compatible inputs and ttl compatible outputs and is packaged in a 128 pin pqfp package.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 8 pin diagram the s/uni-lite is packaged in an 128 pin pqfp package having a body size of 14mm by 20 mm and a pin pitch of 0.50 mm. pin 1 pin 128 pm5346 s/uni-lite top view pin 38 pin 39 pin 64 pin 65 pin 102 pin 103 vss vss vss vss vss vss index pin tbyp atp2 tavd1 tavs1 tavd2 tavs2 trclk- trclk+ tavd3 tavs3 txvdd txc+ txc- txd+ txd- txvss vddo1 vssi1 vddi1 vsso1 rxdo+ rxdo- ravd3 rxd- rxd+ alos- alos+ ravs3 ravd1 ravs1 rrclk- rrclk+ ravs4 ravd2 ravs2 ravd4 atp1 rbyp lfp lfn lfo vss9 vss10 vss11 vss12 vss13 xoff tcp tgfc tfpo tclk vddo2 vsso2 rclk rfp rgfc rcp vddi2 vssi2 ralm vss vss rstb csb vclk rate[0] rate[1] tsoc txprty tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] tca twrenb tfclk rsoc rxprty vddo4 vsso4 rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] vddo3 vsso3 rdat[1] rdat[0] rca rrdenb rfclk tsen wrb rdb vssi3 vddi3 intb d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] ale vddo5 vsso5
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 9 pin description pin name type pin no. function rate1 rate0 input 97 98 the rate1 and rate0 inputs select the frame format and line rate for both transmit and receive: rate[1:0] 11 155.52 mbit/s, sts-3c/stm-1 transmission convergence (tc) 10 51.84 mbit/s, sts-1 tc 01 25.92 mbit/s, sts-1 tc 00 12.96 mbit/s, sts-1 tc the rate1 and rate0 inputs have integral pull up resistors so the default is sts-3c/stm-1. rbyp input 41 the receive bypass (rbyp) input must be tied low for proper operation. rbyp has an integral pull down resistor. rxd+ rxd- pecl input 26 25 the receive differential data inputs (rxd+, rxd-) contain the nrz bit serial receive stream. the receive clock is recovered from the rxd+/- bit stream. rxd+/- must be connected to a differential data source, single-ended operation is not supported for these inputs. rxdo+ rxdo- output 22 23 the receive differential data outputs (rxdo+, rxdo-) are provided to allow decision feedback equalization (dfe) to correct baseline wander. it is intended that these outputs be low pass filtered and attenuated to create an appropriate correction signal that is summed with incoming data to recover the d.c. component. rxdo+/- are retimed (sampled by the recovered clock) versions of the rxd+ and rxd- inputs. rxdo+/- are squelched (rxdo+ is forced low and rxdo- is forced high) when loss of signal (alos+/-) is asserted. rrclk+ rrclk- pecl input 34 33 the receive differential reference clock inputs (rrclk+, rrclk-) contain a jitter-free 19.44 mhz or 6.48 mhz reference clock.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 10 alos+ alos- pecl input 28 27 the analog loss of signal (alos+/-) differential inputs are used to indicate a loss of receive signal power. when alos+/- is asserted, the data on the receive data (rxd+/-) pins will be squelched and the phase locked loop shall switch to the reference clock (rrclk+/-) to keep the recovered clock in range. these inputs must be dc coupled. rclk output 57 the receive clock (rclk) output provides a timing reference for s/uni-lite receive outputs. rclk is a divide by eight of the recovered clock. rgfc, rcp, rfp and ralm are updated on the rising edge of rclk. ralm output 63 the receive alarm (ralm) output indicates the state of the receive framing. ralm is low if no receive alarms are active. ralm is high if line ais, path ais, loss of signal (los), loss of frame (lof), loss of pointer (lop) or loss of cell delineation (lcd) is detected. ralm is updated on the rising edge of rclk. rfp output 58 the receive frame pulse (rfp) output is an 8 khz signal derived from the receive line clock. rfp pulses high for one rclk cycle every 2430 rclk cycles for sts-3c (stm-1) tc mode or every 810 rclk cycles for sts-1 tc mode. rfp is updated on the rising edge of rclk. tbyp input 2 the transmit bypass (tbyp) input must be tied low for proper operation. tbyp has an integral pull down resistor. trclk+ trclk- pecl input 10 9 the transmit differential reference clock inputs (trclk+, trclk-) are a jitter-free 19.44 mhz or 6.48 mhz reference clock. this clock provides timing for the s/uni-lite transmit functions. trclk+/- may be left unconnected when s/uni-lite loop timing is enabled (using the s/uni-lite master control register). txd+ txd- output 15 16 the transmit differential data/positive pulse outputs (txd+, txd-) contain nrz encoded data. txd+/- is updated on the falling edge of txc+/-
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 11 txc+ txc- output 13 14 the transmit clock (txc+, txc-) outputs are available when the transmit data rate is 51.84 mbit/s or less. txd+/- is updated on the falling edge of txc+ and on the rising edge of txc-. when sts-3c tc mode is selected, txc+ is held low and txc- is held high. tfpo output 53 the active high framing position output (tfpo) signal is an 8 khz timing marker for the transmitter. tfpo pulses high for one tclk cycle every 2430 tclk cycles for sts-3c (stm-1) tc mode or every 810 rclk cycles for sts-1 tc mode. tfpo is updated on the rising edge of tclk. tsen input 66 the tristate enable (tsen) input selects the configuration of the receive datapath (rdat[7:0], rsoc). when tsen is tied high, rdat[7:0] operates as a tristate bus controlled by rrdenb. when rrdenb is high upon rfclk rising, rdat[7:0], rxprty and rsoc are tristated. when rrdenb is low upon rfclk rising, rdat[7:0], rxprty and rsoc are enabled. when tsen is tied low, rdat[7:0], rxprty and rsoc are always enabled, regardless of the state of rrdenb. tsen has an integral pull down resistor. rfclk input 67 the receive read clock (rfclk) is used to read atm cells from the receive fifo. rfclk must cycle at a 33 mhz or lower instantaneous rate, but at a high enough rate to avoid fifo overflow. rrdenb is sampled using the rising edge of rfclk. rsoc, rdat[7:0], rxprty and rca are updated on the rising edge of rfclk
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 12 rrdenb input 68 the active low receive read enable input (rrdenb) is used to initiate reads from the receive fifo. when sampled low using the rising edge of rfclk, a byte is read from the internal synchronous fifo and output on bus rdat[7:0] if one is available. when sampled high using the rising edge of rfclk, no read is performed and rdat[7:0] and rsoc is tristated if the tsen input is high. rrdenb must operate in conjunction with rfclk to access the fifo at a high enough instantaneous rate as to avoid fifo overflows. the atm layer device may deassert rrdenb at anytime it is unable to accept another byte. when the rca signal is configured to be deasserted with zero octets (as opposed to four) in the fifo, it is not an error condition to hold the read enable (rrdenb) active. in this situation, the rca signal identifies the valid octets. rdat[0] rdat[1] rdat[2] rdat[3] rdat[4] rdat[5] rdat[6] rdat[7] tristate output 70 71 74 75 76 77 78 79 the receive cell data (rdat[7:0]) bus carries the atm cell octets that are read from the receive fifo. rdat[7:0] is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. the rdat[7:0] bus is always driven when tsen is low, regardless of the level of rrdenb. rxprty tristate output 82 the receive parity (rxprty) signal indicates the parity of the rdat[7:0] bus. odd or even parity selection can be made using a register. rxprty is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. rxprty is always driven when tsen is low, regardless of the level of rrdenb. rsoc tristate output 83 the receive start of cell (rsoc) signal marks the start of cell on the rdat[7:0] bus. when rsoc is high, the first octet of the cell is present on the rdat[7:0] stream. rsoc is updated on the rising edge of rfclk and is tristated when not valid if the tsen input is high. rsoc is always driven when tsen is low, regardless of the level of rrdenb.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 13 rca output 69 the receive cell available (rca) signal indicates when a cell is available in the receive fifo. rca can be configured to be deasserted when either zero or four bytes remain in the fifo. rca is updated on the rising edge of rfclk. the active polarity of this signal is programmable and defaults to active high. rgfc output 59 the receive generic flow control (rgfc) output presents the extracted gfc bits in a serial stream. the four gfc bits are presented for each received cell, with the rcp output indicating the position of the most significant bit. the serial link is forced low if cell delineation is lost. rgfc is updated on the rising edge of rclk. rcp output 60 the receive gfc cell pulse (rcp) indicates the location of the four gfc bits in the rgfc serial stream. rcp is coincident with the most significant gfc bit and is asserted 6 payload octets after the first octet of the cell is written into receive fifo. rcp is updated on the rising edge of rclk. tclk output 54 the transmit byte clock (tclk) is either a 19.44 mhz or a 6.48 mhz clock derived by dividing the transmit line rate by eight. tfclk input 84 the transmit write clock (tfclk) is used to write atm cells to the four cell transmit fifo. tfclk cycles at a 33 mhz or lower instantaneous rate. a complete 53 octet cell must be written to the fifo before being inserted in the synchronous payload envelope (spe). idle/unassigned cells are inserted when a complete cell is not available. tdat[7:0], txprty, twrenb and tsoc are sampled on the rising edge of tfclk. tca is updated on the rising edge of tfclk. tdat[0] tdat[1] tdat[2] tdat[3] tdat[4] tdat[5] tdat[6] tdat[7] input 87 88 89 90 91 92 93 94 the transmit cell data (tdat[7:0]) bus carries the atm cell octets. then the transmit cell data (tdat[7:0]) bus carries the atm cell octets that are written to the transmit fifo. tdat[7:0] is sampled on the rising edge of tfclk and is considered valid only when twrenb is simultaneously asserted.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 14 txprty input 95 the transmit parity (txprty) signal indicates the parity of the tdat[7:0] bus. odd or even parity selection can be made using a register. txprty is sampled on the rising edge of tfclk and is considered valid only when twrenb is simultaneously asserted. txprty has an integral pull down resistor. a parity error is indicated by a status bit and a maskable interrupt. cells with parity errors are not filtered, so the txprty input may be unused. twrenb input 85 the active low transmit write enable input (twrenb) is used to initiate writes to the transmit fifo. when sampled low using the rising edge of tfclk, the byte on tdat[7:0] is written into the transmit fifo. when sampled high using the rising edge of tfclk, no write is performed. a complete 53 octet cell must be written to the transmit fifo before it is inserted into the spe. idle/unassigned cells are inserted when a complete cell is not available. tsoc input 96 the transmit start of cell (tsoc) signal marks the start of cell on the tdat[7:0] bus. when tsoc is high, the first octet of the cell is present on the tdat[7:0] stream. it is not necessary for tsoc to be present at each cell. an interrupt may be generated if tsoc is high during any byte other than the first byte. tsoc is sampled on the rising edge of tfclk tca output 86 the transmit cell available (tca) signal indicates when a cell is available in the transmit fifo. when high, tca indicates that the transmit fifo is not full and a complete cell may be written in. when tca goes low, it indicates either that the transmit fifo is near full and can accept no more than four writes or that the transmit fifo is full. selection is made using a register bit in the tacp fifo control register. to reduce fifo latency, the fifo depth at which tca indicates "full" can be set to one, two, three or four cells by the tacp fifo control register. if the programmed depth is less than four, additional cells may be written after tca is asserted. tca is updated on the rising edge of tfclk. the active polarity of this signal is programmable and defaults to active high.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 15 xoff input 50 the transmit off (xoff) input prevents the insertion of cells from the transmit fifo. if xoff is asserted high, the next cell transmitted is an idle/unassigned cell regardless of the number of cells in the fifo. idle/unassigned cells are transmitted until xoff is deasserted. xoff may be treated as an asynchronous signal. xoff has an integral pull down resistor. tgfc input 52 the transmit generic flow control (tgfc) input provides the ability to insert the gfc value downstream of the fifo. the four tclk periods following the tcp output pulse contain the gfc value to be inserted into the current cell. the gfc enable bits of the tacp configuration register enable the insertion of each serial bit. by default, the gfc values are the contents of the tacp idle/unassigned cell header control register for idle/unassigned cells and the value received from tdat[7:0] for assigned cells. tgfc is sampled on the rising edge of tclk. tcp output 51 the transmit gfc cell pulse (tcp) indicates where the valid tgfc serial bits are expected. if tcp is asserted high, the most significant gfc bit is expected in the subsequent tclk period. tcp pulses high for one tclk for every transmitted cell six payload octets before the first octet of the cell read from the transmit fifo. tcp is updated on the rising edge of tclk. atp1 atp2 analog 40 3 two analog test points (atp1, atp2) are provided for production test purposes. connect these pins to ground. lf+, lf-, lfo analog 42 43 44 passive components connected to the recovery loop filter (lf+, lf- and lfo) pins determine the dynamics of the clock recovery unit. refer to the operation section for details. csb input 100 the active low chip select (csb) signal is low during s/uni-lite register accesses. if csb is not required (i.e. register accesses are controlled using the rdb abd wrb signals only), csb must be connected to an inverted version of the rstb input.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 16 rdb input 105 the active low read enable (rdb) signal is low during s/uni-lite register read accesses. the s/uni-lite drives the d[7:0] bus with the contents of the addressed register while rdb and csb are low. wrb input 104 the active low write strobe (wrb) signal is low during a s/uni-lite register write accesses. the d[7:0] bus contents are clocked into the addressed register on the rising wrb edge while csb is low. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] i/o 109 110 111 112 115 116 117 118 the bidirectional data bus d[7:0] is used during s/uni-lite register read and write accesses. a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7]/trs input 119 120 121 122 123 124 125 126 the address bus a[7:0] selects specific registers during s/uni-lite register accesses. the test register select (trs) signal selects between normal and test mode register accesses. trs is high during test mode register accesses, and is low during normal mode register accesses. trs has an integral pull down resistor. rstb input 101 the active low reset (rstb) signal provides an asynchronous s/uni-lite reset. rstb is a schmitt triggered input with an integral pull up resistor. ale input 127 the address latch enable (ale) is active high and latches the address bus a[7:0] when low. when ale is high, the internal address latches are transparent. it allows the s/uni-lite to interface to a multiplexed address/data bus. ale has an integral pull up resistor.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 17 intb open- drain output 108 the active low interrupt (intb) signal goes low when a s/uni-lite interrupt source is active, and that source is unmasked. the s/uni-lite may be enabled to report many alarms or events via interrupts. intb returns high when the interrupt is acknowledged via an appropriate register access. intb is an open drain output. vclk input 99 the test vector clock (vclk) signal is used during s/uni-lite production testing to verify internal functionality. vclk has an integral pull down resistor. vddi1 vddi2 vddi3 power 20 61 107 the core power (vddi1 - vddi3) pins should be connected to a well decoupled +5 v dc in common with vddo. vssi1 vssi2 vssi3 ground 19 62 106 the core ground (vssi1 - vssi3) pins should be connected to gnd in common with vsso. txvdd power 12 the transmit pad power (txvdd) supplies the txc+/- and txd+/- outputs. txvdd is physically isolated from the other device power pins and should be well regulated +5 v dc and noise free for good performance when driving category 5 unshielded twisted pair cabling. txvss ground 17 the transmit pad ground (txvss) is the return path for the txc+/- and txd+/- outputs. txvss is physically isolated from the other device ground pins and should be noise free for good performance when driving category 5 unshielded twisted pair cabling. vddo1 vddo2 vddo3 vddo4 vddo5 power 18 55 73 81 114 the pad ring power (vddo1 - vddo5) pins should be connected to a well decoupled +5 v dc in common with vddi. vsso1 vsso2 vsso3 vsso4 vsso5 ground 21 56 72 80 113 the pad ring ground (vsso1 - vsso5) pins should be connected to gnd in common with vssi.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 18 vss1, vss2, vss3, vss4, vss5, vss6, vss7, vss8 vss9 vss10 vss11 vss12 vss13 thermal ground 1 38 39 64 65 102 103 128 45 46 47 48 49 the thermal grounds (vss1 - vss13) provide a low thermal resistance for the dissipated heat. these pins must be connected to gnd for correct operation. tavd1 power 4 the power (tavd1) pin for the transmit clock synthesizer reference circuitry. tavd1 should be connected to analog +5v. tavd2 power 6 the power (tavd2) pin for the transmit clock synthesizer oscillator. tavd2 should be connected to analog +5v. tavs1 ground 5 the ground (tavs1) pin for the transmit clock synthesizer reference circuitry. tavs1 should be connected to analog gnd. tavs2 ground 7 the ground (tavs2) pin for the transmit clock synthesizer oscillator. tavs2 should be connected to analog gnd. tavd3 power 8 the power (tavd3) pin for the transmit pecl inputs. tavd3 should be connected to analog +5v. tavs3 ground 11 the ground (tavs3) pin for the transmit pecl inputs. tavs3 should be connected to analog gnd. ravd1 power 30 the power (ravd1) pin for receive clock and data recovery block reference circuitry. ravd1 should be connected to analog +5v. ravd2 power 36 the power (ravd2) pin for receive clock and data recovery block active loop filter and oscillator. ravd2 should be connected to analog +5v. ravs1 ground 31 the ground (ravs1) pin for receive clock and data recovery block reference circuitry. ravs1 should be connected to analog gnd.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 19 ravs2 ground 37 the ground (ravs2) pin for receive clock and data recovery block active loop filter and oscillator. ravs2 should be connected to analog gnd. ravd3 power 24 the power (ravd3) pin for the rxd+/- and alos+/- pecl inputs. ravd3 should be connected to analog +5v. ravd4 power 32 the power (ravd4) pin for the rrclk+/- pecl inputs. ravd4 should be connected to analog +5v. ravs3 ground 29 the ground (ravs3) pin for the rxd+/- and al os+/- pecl inputs. ravs3 should be connected to analog gnd. ravs4 ground 35 the ground (ravs4) pin for the rrclk+/- pecl inputs. ravs4 should be connected to analog gnd. notes on pin description: 1. all s/uni-lite inputs and bidirectionals present minimum capacitive loading and operate at ttl logic levels except for the trclk+, trclk-, rrclk+, rrclk-, rxd+, rxd-, alos+ and alos- differential inputs which operate at pseudo ecl (pecl) logic levels. 2. the rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk, rclk, txd+, txd-, txc+ and txc- outputs have a 8 ma drive capability. all other s/uni-lite digital outputs and bidirectionals have 4 ma drive capability. all 4 ma and 8 ma outputs are slew rate limited except for the txd+, txd-, txc+, and txc- outputs. 3. the vsso and vssi ground pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the s/uni- lite. 4. the vddo and vddi power pins are not internally connected together. failure to connect these pins externally may cause malfunction or damage the s/uni- lite. 5. all analog power and ground pins are sensitive to noise. they must be isolated from the digital power and ground. the tavd2 and ravd2 pins power oscillators; therefore, they generate significant switching noise. care must be taken to decouple these pins from each other and all other analog power and ground pins.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 20 functional description clock recovery the clock recovery unit recovers the clock from the incoming bit serial data stream. the clock recovery unit is fully compliant with sonet and sdh jitter tolerance requirements. the clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery pll. under loss of signal conditions, the clock recovery unit will continue to output a line rate clock that is locked to this reference for keep alive purposes. the clock recovery unit can be configured to utilize reference clocks at 6.48 or 19.44 mhz. the clock recovery unit provides status bits that indicate whether it is locked to data or the reference. the clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data. initially, the pll locks to the reference clock, rrclk+/-. when the frequency of the recovered clock is within 244 ppm of the reference clock, the pll attempts to lock to the data. once in data lock, the pll reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 244 ppm of the reference clock. when the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the rrclk+/- reference accuracy in the case of a loss of signal condition. to meet the gr-253-core sonet network element free-run accuracy specification, the reference must be within +/-20ppm. when not loop timed, the rrclk+/- accuracy may be relaxed to +/-50ppm. the loop filter transfer function is optimized to enable the pll to track the jitter, yet tolerate the minimum transition density expected in a received sonet data signal. the total loop dynamics of the clock recovery pll yield a jitter tolerance which exceeds the minimum tolerance required for sonet equipment by gr-253-core (figure 2).
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 21 fig. 2 sts-3c/stm-1jitter tolerance jitter freq. (hz) 0.1 1 10 100 100 1000 10000 100000 1000000 10000000 gr-253-core note that for frequencies below 300 hz the jitter tolerance is greater than 15 uipp; 15 uipp is the maximum jitter tolerance of the test equipment. also note that the dip in the tolerance curve between 300 hz and 10 khz is due to the s/uni-lite's internal clock difference detector: if the recovered clock drifts beyond 244 ppm of the reference, the pll locks to the reference clock. the typical jitter tolerance illustrated in figure 2 is associated with the external loop filter components illustrated in figure 14a. serial to parallel converter the serial to parallel converter (sipo) converts the received bit serial sonet stream to a byte serial stream. the sipo searches for the sonet/sdh framing pattern (a1, a2 ) in the incoming stream, and performs serial to parallel conversion on octet boundaries. receive section overhead processor the receive section overhead processor (rsop) provides frame synchronization, descrambling, section level alarm and performance monitoring. framer the framer block determines the in-frame/out-of-frame status of the sts-3c or sts-1 data stream. output ralm reflects this status, and is updated with timing aligned to rclk.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 22 while in-frame, the framing bytes (a1, a2) in each frame are compared against the expected pattern. out-of-frame is declared when four consecutive frames containing one or more framing pattern errors have been received. while out-of-frame, the sipo block monitors the bit serial data stream for an occurrence of the framing pattern. when a framing pattern has been recognized, the framer block verifies that an error free framing pattern is present in the next frame before declaring in-frame. descramble the descramble block utilizes a frame synchronous descrambler to process the received byte serial stream. the generating polynomial is 1 + x 6 + x 7 and the sequence length is 127. details of the descrambling operation are provided in the references. note that the framing bytes (a1 and a2) and the identity bytes (c1) are not descrambled. a register bit is provided to disable the descrambling operation. error monitor the error monitor block calculates the received section bip-8 error detection code (b1) based on the scrambled data of the complete sts-3c or sts-1 frame. the section bip-8 code is based on a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip-8 code is compared with the bip-8 code extracted from the b1 byte of the following frame. differences indicate that a section level bit error has occurred. up to 64000 (8 x 8000) bit errors can be detected per second. the error monitor block accumulates these section level bit errors in a 16 bit saturating counter that can be read via the microprocessor interface. circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. it is intended that this counter be polled at least once per second so as not to miss bit error events. loss of signal the loss of signal block monitors the scrambled data of the complete sts-3c or sts-1 stream for the absence of 1's. when 20 3 m s of all zeros patterns is detected, a loss of signal (los) is declared. loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. the loss of signal condition asserts the ralm output with timing aligned to rclk. loss of frame the loss of frame block monitors the in-frame / out-of-frame status of the framer block. a loss of frame (lof) is declared when an out-of-frame (oof) condition persists for 3 ms. to provide for intermittent out-of-frame conditions, the 3 ms timer
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 23 is not reset to zero until an in-frame condition persists for 3 ms. the loss of frame is cleared when an in frame condition persists for a period of 3 ms. the loss of frame condition asserts the ralm output with timing aligned to rclk. receive line overhead processor the receive line overhead processor (rlop) provides line level alarm and performance monitoring. line remote defect indication detect the line rdi detect block detects the presence of line remote defect indication (rdi) in the data stream. line rdi is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the k2 byte, for five consecutive frames. line rdi is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. the line rdi status is available through a maskable interrupt and register bits. line ais detect the line ais block detects the presence of a line alarm indication signal (ais) in the data stream. line ais is declared when a 111 binary pattern is detected in bits 6,7,8 of the k2 byte, for five consecutive frames. lais is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the k2 byte for five consecutive frames. line ais detection asserts the ralm output with timing aligned to rclk. error monitor the error monitor block calculates the received line bip-8/24 error detection code (b2) based on the line overhead and synchronous payload envelope of the data stream. the line bip-8/24 code is a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip code is compared with the bip-8/24 code extracted from the b3 byte(s) of the following frame. any differences indicate that a line layer bit error has occurred. up to 192000 (24 x 8000) bit errors can be detected per second. the error monitor block accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. during a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). note, this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events. the error monitor block also accumulates line far end block error indications (contained in the z2 byte) in a similar manner.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 24 receive path overhead processor the receive path overhead processor (rpop) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm and performance monitoring. pointer interpreter the pointer interpreter interprets the incoming pointer (h1, h2) as specified in the references. the pointer value is used to determine the location of the path overhead (the j1 byte) in the incoming sts-3c (au4) or sts-1 (au3) stream. the pointer interpreter block detects loss of pointer (lop) in the incoming sts-1 or sts-3c. lop is declared as a result of eight consecutive invalid pointers or eight consecutive ndf enabled indications. lop is removed when the same valid pointer with normal ndf is detected for three consecutive frames. the pointer interpreter block detects path ais in the incoming sts-1 or sts-3c stream. pais is declared on entry to the ais_state after three consecutive ais indications. pais is removed when the same valid pointer with normal ndf is detected for three consecutive frames or when a valid with ndf enabled is detected. the pointer value is used to extract the path overhead from the incoming stream. note that due to anomalies in the standard pointer interpretation rules, certain illegal pointers may not cause the device to declare a loss of pointer (lop) state. in this situation, however, the device will declare a loss of cell delineation state and return to normal operation when presented with legal pointer values. such illegal pointers typically can only be generated continuously by test equipment and will not normally occur during live-traffic operation. error monitor the error monitor block contains two 16-bit counters that are used to accumulate path bip-8 errors (b3), and far end block errors (febe). the contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. path bip-8 errors are detected by comparing the path bip-8 byte (b3) extracted from the current frame, to the path bip-8 computed for the previous frame. febes are detected by extracting the 4-bit febe field from the path status byte (g1). the legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. any other value is interpreted as zero errors.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 25 path remote defect indication (rdi) is detected by extracting bit 5 of the path status byte. path rdi is declared when bit 5 is set high for five consecutive frames and is cleared when bit 5 is low for five consecutive frames. receive atm cell processor the receive atm cell processor (racp) performs atm cell delineation, provides cell filtering based on idle/unassigned cell detection and hcs error detection, and performs atm cell payload descrambling. the racp also provides a four cell deep receive fifo. this fifo passes a 53 byte data structure and is used to separate the line timing from the higher layer atm system timing. cell delineation cell delineation is the process of framing to atm cell boundaries using the header check sequence (hcs) field found in the cell header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. when performing delineation, correct hcs calculations are assumed to indicate cell boundaries. cells must be byte aligned before insertion in the synchronous payload envelope. the cell delineation algorithm searches the 53 possible cell boundary candidates one at a time to determine the valid cell boundary location. while searching for the cell boundary location, the cell delineation circuit is in the hunt state. when a correct hcs is found, the cell delineation state machine locks on the particular cell boundary and enters the presync state. this state validates the cell boundary location. if the cell boundary is invalid then an incorrect hcs will be received within the next delta cells, at which point a transition back to the hunt state is executed. if no hcs errors are detected in this presync period then the sync state is entered. while in the sync state, synchronization is maintained until alpha consecutive incorrect hcs patterns are detected. in such an event a transition is made back to the hunt state. the state diagram of the delineation process is shown in figure 3.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 26 fig. 3 cell delineation state diagram hunt presync sync correct hcs (byte by byte) delta consecutive correct hcs's (cell by cell) incorrect hcs (cell by cell) alpha consecutive incorrect hcs's (cell by cell) the values of alpha and delta determine the robustness of the delineation method. alpha determines the robustness against false misalignments due to bit errors. delta determines the robustness against false delineation in the synchronization process. alpha is chosen to be 7 and delta is chosen to be 6. these values result in a maximum average time to delineate of 31 m s for sts-3c and 93 m s for sts-1. descrambler the self synchronous descrambler operates on the 48 byte cell payload only. the circuitry descrambles the information field using the 'x 43 + 1' polynomial. the descrambler is disabled for the duration of the header and hcs fields, and may optionally be disabled. cell filter and hcs verification cells are filtered (or dropped) based on hcs errors and/or a cell header pattern. cell filtering is optional and is enabled through the racp registers. cells are passed to the receive fifo while the cell delineation state machine is in the sync state as described above. when both filtering and hcs checking are enabled, cells are dropped if uncorrectable hcs errors are detected, or if the corrected header contents match the pattern contained in the 'match header pattern' and 'match header mask' registers. idle or unassigned cell filtering is accomplished by writing
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 27 the appropriate cell header pattern into the 'match header pattern' and 'match header mask' registers. idle/unassigned cells are assumed to contain the all zeros pattern in the vci and vpi fields. the 'match header pattern' and 'match header mask' registers allow filtering control over the contents of the gfc, pti, and clp fields of the header. the hcs is a crc-8 calculation over the first 4 octets of the atm cell header. the racp block verifies the received hcs using the polynomial, x 8 + x 2 + x + 1. the coset polynomial, x 6 + x 4 + x 2 + 1 is added (modulo 2) to the received hcs octet before comparison with the calculated result. while the cell delineation state machine (described above) is in the sync state, the hcs verification circuit implements the state machine shown in figure 4: fig. 4 hcs verification state diagram detection mode atm delineation sync state correction mode no errors detected (pass cell) apparant multi-bit error (drop cell) errors detected (drop cell) no errors detected (pass cell) alpha consecutive incorrect hcs's (to hunt state) delta consecutive correct hcs's (from presync state) single bit error (correct error and pass cell) in normal operation, the hcs verification state machine remains in the 'correction mode' state. incoming cells containing no hcs errors are passed to the receive fifo. incoming single bit errors are corrected, and the resulting cell is passed to the fifo. upon detection of a single bit error or a multi bit error, the state machine transitions to the 'detection mode' state. in this state, the detection of any hcs error
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 28 causes the corresponding cell to be dropped. cells containing an error-free hcs are passed, and the state machine transitions back to the 'correction mode' state. performance monitor the performance monitor consists of two 8-bit saturating hcs error event counters and a 19-bit cell counter. one of the counters accumulates correctable hcs errors (i.e. single hcs bit errors detected while the hcs verification state machine is in the 'correction mode' state described above). the second counter accumulates uncorrectable hcs errors (i.e. hcs bit errors detected while the hcs verification state machine is in the 'detection mode' state or multiple hcs bit errors detected while the state machine is in the 'correction mode' state as described above). the cell counter accumulates the number of received assigned cells. all counters are enabled only when the racp is in the sync state. each counter may be read through the microprocessor interface. circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. it is intended that the counters be polled at least once per second so hcs error events or cell counts will not be missed. gfc extraction port the gfc extraction port outputs the received gfc bits in a serial stream. the four gfc bits are presented for each received cell, with the rcp output indicating the position of the most significant bit. the updating of rgfc by particular gfc bits may be disabled through an internal register. the serial link is forced low if cell delineation is lost. receive fifo the receive fifo provides fifo management and the asynchronous interface between the racp block and chip pads to the external environment. the receive fifo can accommodate four cells. the receive fifo provides for the separation of the sts-1 or sts-3c line or physical layer timing from the atm layer timing. management functions include filling the receive fifo, indicating when cells are available to be read from the receive fifo, maintaining the receive fifo read and write pointers, and detecting fifo overrun and underrun conditions. upon detection of an overrun condition, the fifo is automatically reset. up to four cells may be lost during the fifo reset operation. upon detection of an underrun, the offending read is ignored. fifo overruns are indicated through a maskable interrupt and register bit. the interface provided indicates the start of a cell (rsoc) when data is read from the receive fifo (using rfclk) and indicates the cell available status (rca).
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 29 the cell available status may be configured to change from available to unavailable on read cell boundaries or four reads before the cell boundary. when the rca signal is configured to be deasserted with zero octets (as opposed to four) in the fifo, it is not an error condition to hold the read enable (rrdenb) active. in this situation, the rca signal identifies the valid octets. clock synthesis the transmit clock is synthesized from a 19.44 mhz or 6.48 mhz reference. the transfer function yields a typical low pass corner of 500 khz with a 19.44 mhz reference and 170 khz with a 6.48 mhz reference, above which reference jitter is attenuated at 12db per octave. the intrinsic jitter is minimised when the reference frequency is 19.44 mhz. with a jitter free 19.44 mhz differential reference input and a low noise board layout, the intrinsic jitter is typically less than 0.01 ui rms when measured using a high pass filter with a 12 khz cutoff frequency. the trclk+/- reference frequency must be within +/-20 ppm of 155.52 mhz to meet the bellcore gr-253-core sonet network element free-run accuracy specification. parallel to serial converter the parallel to serial converter (piso) converts the internal byte serial stream to a bit serial stream. transmit section overhead processor the transmit section overhead processor (tsop) provides frame pattern insertion (a1, a2), scrambling, section level alarm signal insertion, and section bip-8 (b1) insertion. line ais insert line ais insertion results in all bits of the sonet/sdh frame being set to 1 before scrambling except for the section overhead. the line ais insert block substitutes all ones as described when enabled through an internal register accessed through the microprocessor interface. activation or deactivation of line ais insertion is synchronized to frame boundaries. bip-8 insert the bip-8 insert block calculates and inserts the bip-8 error detection code (b1) into the unscrambled data stream.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 30 the bip-8 calculation is based on the scrambled data of the complete sts-3c or sts-1 frame. the section bip-8 code is based on a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip-8 code is then inserted into the b1 byte of the following frame before scrambling. bip- 8 errors may be continuously inserted under register control for diagnostic purposes. framing and identity insert the framing and identity insert block inserts the framing bytes (a1, a2) and identity bytes (c1) into the sts-3c or sts-1 frame. framing bit errors may be continuously inserted under register control for diagnostic purposes. scrambler the scrambler block utilizes a frame synchronous scrambler to process the transmit serial stream when enabled through an internal register accessed via the microprocessor interface. the generating polynomial is 1 + x 6 + x 7 . precise details of the scrambling operation are provided in the references. note that the framing bytes and the identity bytes are not scrambled. all zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. transmit line overhead processor the transmit line overhead processor (tlop) provides line level alarm signal insertion, and line bip-8/24 insertion (b2). bip calculate the bip calculate block calculates the line bip error detection code (b2) based on the line overhead and synchronous payload envelope of the sts-3c or sts-1 stream. the line bip code is a bit interleaved parity calculation using even parity. details are provided in the references. the calculated bip code is inserted into the b2 byte positions of the following frame. bip errors may be continuously inserted under register control for diagnostic purposes. line remote defect indication insert the line rdi insert block multiplexes the line overhead bytes into the output stream and optionally inserts line rdi. line rdi is inserted by this block when enabled via register control. line rdi is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the k2 byte contained in the sts-3c or sts-1 stream.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 31 line febe insert the line febe insert block accumulates line bip errors (z2) detected by the receive line overhead processor and encodes far end block error indications in the transmit z2 byte. fig. 5 sts-3c/stm-1 default transport overhead values c1 (0x01) c1 (0x02) c1 (0x03) a2 (0x28) a2 (0x28) a2 (0x28) a1 (0xf6) f1 (0x00) (0x00) (0x00) e1 (0x00) (0x00) (0x00) b1 (*) (0x00) (0x00) d3 (0x00) (0x00) (0x00) d2 (0x00) (0x00) (0x00) d1 (0x00) (0x00) (0x00) h3 (0x00) h3 (0x00) h3 (0x00) h2 (0x0a) h2 (0xff) h2 (0xff) h1 (0x62) h1 (0x93) h1 (0x93) k2 (0x00) (0x00) (0x00) k1 (0x00) (0x00) (0x00) b2 (*) b2 (*) b2 (*) d6 (0x00) (0x00) (0x00) d5 (0x00) (0x00) (0x00) d4 (0x00) (0x00) (0x00) d9 (0x00) (0x00) (0x00) d8 (0x00) (0x00) (0x00) d7 (0x00) (0x00) (0x00) d12 (0x00) (0x00) (0x00) d11 (0x00) (0x00) (0x00) d10 (0x00) (0x00) (0x00) e2 (0x00) (0x00) (0x00) z2 (0x00) z2 (0x00) z2 (*) z1 (0x00) z1 (0x00) z1 (0x00) * : b1, b2 values depend on payload contents z2 value depends on incoming line bit errors a1 (0xf6) a1 (0xf6)
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 32 fig. 6 sts-1 default transport overhead values c1 (0x01) a2 (0x28) f1 (0x00) e1 (0x00) b1 (*) d3 (0x00) d2 (0x00) d1 (0x00) h3 (0x00) h2 (0x0a) h1 (0x62) k2 (0x00) k1 (0x00) b2 (*) d6 (0x00) d5 (0x00) d4 (0x00) d9 (0x00) d8 (0x00) d7 (0x00) d12 (0x00) d11 (0x00) d10 (0x00) e2 (0x00) z2 (*) z1 (0x00) a1 (0xf6) * : b1, b2 values depend on payload contents z2 value depends on incoming line bit errors transmit path overhead processor the transmit path overhead processor (tpop) provides transport frame alignment generation, pointer generation (h1, h2), path overhead insertion, insertion of the synchronous payload envelope, insertion of path level alarm signals and path bip-8 (b3) insertion. pointer generator the pointer generator block generates the outgoing payload pointer (h1, h2). the block contains a free running timeslot counter that locates the start of the synchronous payload envelope based on the generated pointer value and the sonet/sdh frame alignment.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 33 the pointer generator block generates the outgoing pointer as specified in the references. the concatenation indication (the ndf field set to 1001, i-bits and d-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer bytes. bip-8 calculate the bip-8 calculate block performs a path bit interleaved parity calculation on the spe of the outgoing stream. the resulting parity byte is inserted in the path bip-8 (b3) byte position of the subsequent frame. bip-8 errors may be continuously inserted under register control for diagnostic purposes. febe calculate the febe calculate block accumulates far end block errors on a per frame basis, and inserts the accumulated value (up to maximum value of eight) in the febe bit positions of the path status (g1) byte. the febe information is derived from path bip-8 errors detected by the receive path overhead processor, rpop. the asynchronous nature of these signals implies that more than eight febe events may be accumulated between transmit g1 bytes. if more than eight receive path bip-8 errors are accumulated between transmit g1 bytes, the accumulation counter is decremented by eight, and the remaining febes are transmitted at the next opportunity. far end block errors may be inserted under register control for diagnostic purposes. spe multiplexer the spe multiplexer block multiplexes the payload pointer bytes, the spe stream, and the path overhead bytes into the sts-3c or sts-1 stream.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 34 fig. 7 default path overhead values j1 (0x00) b3 (*) c2 (0x13) z3 (0x00) z4 (0x00) z5 (0x00) f2 (0x00) h4 (*) * : b3 value depend on payload contents g1 value depends on incoming path bit errors h4 value depends on cell boundary offset g1 (*) transmit atm cell processor the transmit atm cell processor (tacp) inserts h4 framing, provides rate adaptation via idle/unassigned cell insertion, provides hcs generation and insertion, and performs atm cell scrambling. the tacp contains a four cell transmit fifo. an idle or unassigned cell is transmitted if a complete atm cell has not been written into the fifo. idle/unassigned cell generator the idle/unassigned cell generator inserts idle or unassigned cells into the cell stream when enabled. registers are provided to program the gfc, pti, and clp fields of the idle cell header and the idle cell payload. an all zeros pattern is
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 35 inserted into the vci/vpi bit locations. the idle cell hcs is automatically calculated and inserted. scrambler the scrambler scrambles the 48 octet information field. scrambling is performed using a parallel implementation of the self synchronous scrambler described in the references. the cell headers are transmitted unscrambled, and the scrambler may optionally be completely disabled. hcs generator the hcs generator performs a crc-8 calculation over the first four header octets. a parallel implementation of the polynomial, x 8 +x 2 +x+1 is used. the coset polynomial, x 6 +x 4 +x 2 +1 is added (modulo 2) to the residue. the hcs generator inserts the result into the fifth octet of the header. gfc insertion port the gfc insertion port provides the ability to insert the gfc value downstream of the fifo. the four gfc bits are received on a serial stream the is synchronized to the transmit cell by a framing pulse. the gfc enable register bits control the insertion of each serial bit. if the enable is cleared, the default gfc value is inserted. for idle/unassigned cells, the default is the contents of the tacp idle/unassigned cell header control register. for assigned cells, the default is the value received from tdat[7:0]. transmit fifo the transmit fifo provides fifo management and a synchronous interface between the s/uni-lite device and the external environment. the transmit fifo can accommodate four cells. it provides for the separation of the physical layer timing from the atm layer timing. management functions include filling the transmit fifo, indicating when cells are available to be written to the transmit fifo, maintaining the transmit fifo read and write pointers, and detecting a fifo overrun condition. the synchronous interface provided to an external device expects the start of a cell (tsoc) when the first byte of the cell is written to the fifo (using tfclk in conjunction with twrenb) and indicates the cell available status (tca). the fifo status changes from cell unavailable to cell available on read cell boundaries. the fifo status can be configured to change from cell available to cell unavailable on write cell boundaries or four octets before the end of the cell. the latency through the transmit fifo can be controlled by setting the fill level at which the cell available (tca) signal is deasserted. although all four cell buffers are
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 36 always accessible, tca may be programmed to indicate when the fifo contains one, two, three or four cells. (the current cell being read out of the fifo is included in the count. be aware that setting a depth of one may limit throughput.) if a cell write is started immediately after tca is asserted, the latency through the device for sts-3c/stm-1 is latency = depth*(53 line byte periods) + 16 line byte periods (min.) = depth*(53 line byte periods) + 26 line byte periods (max.). the latency for sts-1 is latency = depth*(53 line byte periods) + 10 line byte periods (min.) = depth*(53 line byte periods) + 14 line byte periods (max.). the presence of the sonet/sdh overhead accounts for the difference between the minimum and maximum latencies. when the fifo contains four cells and the upstream device writes into the fifo, the tacp indicates a fifo overrun condition using a maskable interrupt and register bits. the offending write and all subsequent writes are ignored until there is room in the fifo. drop side interface receive interface the drop side receive interface can be accessed through a generic 8-bit wide interface. external circuitry is notified, using the rca signal, when a cell is available in the receive fifo. external circuitry may then read the cell from the buffer as a byte wide stream (along with a bit marking the first byte of the cell) at instantaneous rates of up to 33 mhz. transmit interface the drop side transmit interface can be accessed through a generic 8-bit wide interface. external circuitry is notified, using the tca signal, when a cell may be written to the transmit fifo. the cell is written to the fifo as a byte wide stream (along with a bit marking the first byte of the cell) at instantaneous rates of up to 33 mhz.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 37 microprocessor interface the microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. the normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the s/uni-lite. the register set is accessed as follows:
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 38 register memory map address register 0x00 s/uni-lite master reset and identity / load meters 0x01 s/uni-lite master configuration 0x02 s/uni-lite master interrupt status 0x04 s/uni-lite master clock monitor 0x05 s/uni-lite master control 0x06 s/uni-lite clock synthesis control and status 0x07 s/uni-lite clock recovery control and status 0x08-0x0b reserved 0x0c-0x0f reserved 0x10 rsop control/interrupt enable 0x11 rsop status/interrupt status 0x12 rsop section bip-8 lsb 0x13 rsop section bip-8 msb 0x14 tsop control 0x15 tsop diagnostic 0x16-0x17 tsop reserved 0x18 rlop control/status 0x19 rlop interrupt enable/status 0x1a rlop line bip-8/24 lsb 0x1b rlop line bip-8/24 0x1c rlop line bip-8/24 msb 0x1d rlop line febe lsb 0x1e rlop line febe 0x1f rlop line febe msb 0x20 tlop control 0x21 tlop diagnostic 0x22-0x23 tlop reserved 0x24-0x27 reserved 0x28-0x2b reserved 0x2c-0x2f reserved 0x30 rpop status/control 0x31 rpop interrupt status 0x32 rpop reserved 0x33 rpop interrupt enable 0x34 rpop reserved 0x35 rpop reserved 0x36 rpop reserved 0x37 rpop path signal label
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 39 0x38 rpop path bip-8 lsb 0x39 rpop path bip-8 msb 0x3a rpop p ath febe lsb 0x3b rpop path febe msb 0x3c rpop reserved 0x3d rpop path bip-8 configuration 0x3e-0x3f rpop reserved 0x40 tpop control/diagnostic 0x41 tpop pointer control 0x42 tpop reserved 0x43 tpop reserved 0x44 tpop reserved 0x45 tpop arbitrary pointer lsb 0x46 tpop arbi trary pointer msb 0x47 tpop reserved 0x48 tpop path signal label 0x49 tpop path status 0x4a tpop reserved 0x4b-0x4f tpop reserved 0x50 racp control/status 0x51 racp interrupt enable/status 0x52 racp match header pattern 0x53 racp match header mask 0x54 racp correctable hcs error count 0x55 racp uncorrectable hcs error count 0x56 racp receive cell counter (lsb) 0x57 racp receive cell counter 0x58 racp receive cell counter (msb) 0x59 racp configuration 0x5a-0x5f racp reserved 0x60 tacp control/status 0x61 tacp idle/unassigned cell header pattern 0x62 tacp idle/unassigned cell payload octet pattern 0x63 tacp fifo configuration 0x64 tacp transmit cell counter (msb) 0x65 tacp transmit cell counter (msb) 0x66 tacp transmit cell counter (msb) 0x67 tacp configuration 0x68-0x7f reserved 0x80 s/uni-lite master test 0x81-0xff reserved for test
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 40 normal mode register description normal mode registers are used to configure and monitor the operation of the s/uni-lite. normal mode registers (as opposed to test mode registers) are selected when trs (a[7]) is low. notes on normal mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. all configuration bits that can be written into can also be read back. this allows the processor controlling the s/uni-lite to determine the programming state of the block. 3. writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. writing into read-only normal mode register bit locations does not affect s/uni- lite operation unless otherwise noted. 5. certain register bits are reserved. these bits are associated with megacell functions that are unused in this application. to ensure that the s/uni-lite operates as intended, reserved register bits must only be written with logic zero. similarly, writing to reserved registers should be avoided.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 41 register 0x00: s/uni-lite master reset and identity / load meters bit type function default bit 7 r/w reset 0 bit 6 r type[2] 0 bit 5 r type[1] 1 bit 4 r type[0] 1 bit 3 r id[3] 0 bit 2 r id[2] 0 bit 1 r id[1] 0 bit 0 r id[0] 0 this register allows the revision of the s/uni-lite to be read by software permitting graceful migration to support for newer, feature enhanced versions of the s/uni- lite. it also provides software reset capability. writing this register loads all the error counters in the rsop, rlop, rpop, racp and tacp blocks. id[3:0]: the id bits can be read to provide a binary s/uni-lite revision number. type[2:0]: the type bits distinguish the s/uni-lite from the other members of the s/uni family of devices. reset: the reset bit allows the s/uni-lite to be reset under software control. if the reset bit is a logic one, the entire s/uni-lite is held in reset. this bit is not self-clearing. therefore, a logic zero must be written to bring the s/uni- lite out of reset. holding the s/uni-lite in a reset state places it into a low power, stand-by mode. a hardware reset clears the reset bit, thus negating the software reset. otherwise the effect of a software reset is equivalent to that of a hardware reset.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 42 register 0x01: s/uni-lite master configuration bit type function default bit 7 unused x bit 6 r/w autofebe 1 bit 5 r/w autolrdi 1 bit 4 r/w autoprdi 1 bit 3 r/w tcainv 0 bit 2 r/w rcainv 0 bit 1 r/w rxdinv 0 bit 0 unused x rxdinv: the rxdinv bit selects the active polarity of the rxd+/- signals. the default configuration selects rxd+ to be active high and rxd- to be active low. when rxdinv is set to logic one, rxd+ to be active low and rxd- to be active high. rcainv: the rcainv bit selects the active polarity of the rca signal. the default configuration selects rca to be active high, indicating that a received cell is available when high. when rcainv is set to logic one, the rca signal becomes active low. tcainv: the tcainv bit selects the active polarity of the tca signal. the default configuration selects tca to be active high, indicating that a cell is available in the transmit fifo when high. when tcainv is set to logic one, the tca signal becomes active low. autoprdi the autoprdi bit determines whether sts path remote defect indication (rdi) is sent immediately upon detection of an incoming alarm. when autoprdi is set to logic one, sts path rdi is inserted immediately upon declaration of loss of signal (los), loss of frame (lof), line ais, loss of pointer (lop), sts path ais or loss of cell delineation (lcd). autolrdi the autolrdi bit determines whether line remote defect indication (rdi) is sent immediately upon detection of an incoming alarm. when autolrdi is set to logic one, line rdi is inserted immediately upon declaration of loss of signal (los), loss of frame (lof) or line ais.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 43 autofebe the autofebe bit determines whether line and path far end block errors are sent upon detection of an incoming line and path bip error events. when autofebe is set to logic one, one line or path febe is inserted for each line or path bip error event, respectively. when autofebe is set to logic zero, incoming line or path bip error events do not generate febe events.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 44 register 0x02: s/uni-lite master interrupt status bit type function default bit 7 r trooli x bit 6 r lcdi x bit 5 r rdooli x bit 4 r tacpi x bit 3 r racpi x bit 2 r rpopi x bit 1 r rlopi x bit 0 r rsopi x this register allows the source of an active interrupt to be identified down to the block level. further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. rsopi: the rsopi bit is high when an interrupt request is active from the rsop block. the rsop interrupt sources are enabled in the rsop control/interrupt enable register. rlopi: the rlopi bit is high when an interrupt request is active from the rlop block. the rlop interrupt sources are enabled in the rlop interrupt enable/status register. rpopi: the rpopi bit is high when an interrupt request is active from the rpop block. the rpop interrupt sources are enabled in the rpop interrupt enable register. racpi: the racpi bit is high when an interrupt request is active from the racp block. the racp interrupt sources are enabled in the racp interrupt enable/status register. tacpi: the tacpi bit is high when an interrupt request is active from the tacp block. the tacp interrupt sources are enabled in the tacp interrupt control/status register. trooli: the trooli bit is the transmit reference out of lock interrupt status bit. trooli is set high when the troolv bit of the s/uni-lite clock synthesis
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 45 control and status register changes state. troolv indicates the clock synthesis phase locked loop is unable to lock to the reference on rrclk+/- and is a logic one if the divided down synthesized clock frequency not within 244ppm of the trclk+/- frequency. trooli is cleared when this register is read. lcdi: the lcdi interrupt bit is set high when entering and exiting loss of cell delineation. this bit is reset immediately after a read to this register. the lcd interrupt is enabled in the s/uni-lite master control register. rdooli: the rdooli bit is the receive data out of lock interrupt status bit. rdooli is set high when the rdoolv bit of the s/uni-lite clock recovery control and status register changes state. rdoolv is a logic one if the divided down recovered clock frequency not within 244ppm of the rrclk+/- frequency or if no transitions have occurred on the rxd+/- inputs for more than 80 bit periods. rdooli is cleared when this register is read.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 46 register 0x04: s/uni-lite master clock monitor bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r rrclka x bit 2 r trclka x bit 1 r rclka x bit 0 r tclka x this register provides activity monitoring on s/uni-lite clocks. when a monitored clock signal makes a low to high transition, the corresponding register bit is set high. the bit will remain high until this register is read, at which point, all the bits in this register are cleared. a lack of transitions is indicated by the corresponding register bit reading low. this register should be read at periodic intervals to detect clock failures. tclka: the tclk active (tclka) bit monitors for low to high transitions on the tclk output. tclka is set high on a rising edge of tclk, and is set low when this register is read. rclka: the rclk active (rclka) bit monitors for low to high transitions on the rclk output. rclka is set high on a rising edge of rclk, and is set low when this register is read. trclka: the trclk active (trclka) bit monitors for low to high transitions on the trclk+ and trclk- inputs. trclka is set high on a rising edge of trclk+, and is set low when this register is read. rrclka: the rrclk active (rrclka) bit monitors for low to high transitions on the rrclk+ and rrclk- inputs. rrclka is set high on a rising edge of rrclk+, and is set low when this register is read.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 47 register 0x05: s/uni-lite master control bit type function default bit 7 r/w lcde 0 bit 6 r lcdv x bit 5 r/w fixptr 1 bit 4 unused x bit 3 unused x bit 2 r/w lle 0 bit 1 r/w dle 0 bit 0 r/w loopt 0 this register controls the timing and high speed loopback features of the s/uni- lite. loopt: the loopt bit selects the source of timing for the transmit section of the s/uni-lite. when loopt is a logic zero, the transmitter timing is derived from inputs trclk+ and trclk-. when loopt is a logic one, the transmitter timing is derived from the receiver inputs rxd+ and rxd- when clock recovery is enabled and from rrclk+ and rrclk- when clock recovery is disabled. dle: the dle bit enables the s/uni-lite diagnostic loopback. when dle is a logic one, the transmit stream is connected to the receive stream. the dle and the lle bits should not be both set to a iogic one simultaneously. lle: the lle bit enables the s/uni-lite line loopback. when lle is a logic one, rxd+ and rxd- are connected internally to txd+ and txd-, respectively. the dle and the lle bits should not be both set to a iogic one simultaneously. fixptr: the fixptr bit disables transmit payload pointer adjustments. if the fixptr bit is a logic 1, the transmit payload pointer is set at 522. if fixptr is a logic zero, the payload pointer is controlled by the contents of the tpop pointer control register. lcdv: the lcdv bit reflects the current loss of cell delineation state. lcdv becomes a logic 1 when an out of cell delineation state has persisted for 4ms
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 48 without any lower level alarms (los, lop, path ais, line ais) occurring. lcdv becomes logic 0 when the sync state has been maintained for 4ms. lcde: the lcde bit enables the loss of cell delineation (lcd) interrupt. when logic one, the s/uni-lite intb output is asserted when there is a change in the lcd state. when logic zero, the s/uni-lite intb output is not affected by the change in lcd state.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 49 register 0x06: s/uni-lite clock synthesis control and status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r troolv x bit 2 unused x bit 1 r/w troole 0 bit 0 r/w trefsel 0 this register controls the clock synthesis and reports the state of the transmit phase locked loop. trefsel: the transmit reference select (trefsel) bit determines the expected frequency of trclk+/-. if trefsel is a logic 0, the correct line clock frequency is synthesized if the reference frequency is 19.44 mhz. if trefsel is a logic 1, the reference frequency must be 6.48 mhz. trefsel only has effect if the tbyp input is deasserted low. troole: the troole bit is an interrupt enable for the transmit reference out of lock status. when troole is set to logic one, an interrupt is generated when the troolv bit changes state. troolv: the transmit reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference on trclk+/-. troolv is a logic one if the divided down synthesized clock frequency not within 244ppm of the trclk+/- frequency.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 50 register 0x07: s/uni-lite clock recovery control and status bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 r rroolv x bit 3 r rdoolv x bit 2 unused x bit 1 r/w rdoole 0 bit 0 r/w rrefsel 0 this register controls the clock recovery and reports the state of the receive phase locked loop. rrefsel: the receive reference select (rrefsel) bit determines the expected frequency of rrclk+/-. if rrefsel is a logic 0, the reference frequency is 19.44 mhz. if rrefsel is a logic 1, the reference frequency must be 6.48 mhz. rrefsel only has effect if the rbyp input is deasserted low. rdoole: the rdoole bit is an interrupt enable for the receive data out of lock status. when rdoole is set to logic one, an interrupt is generated when the rdoolv bit changes state. rdoolv: the receive data out of lock status indicates the clock recovery phase locked loop is unable to lock to the incoming data stream. rdoolv is a logic one if the divided down recovered clock frequency is not within 244ppm of the rrclk+/- frequency or if no transitions have occurred on the rxd+/- inputs for more than 80 bit periods. rroolv: the receive reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the receive reference (rrclk+/-). rroolv should be polled after a power up reset to determine when the cru pll is operational. when rroolv is a logic 1, the cru is unable to lock to the receive reference. when rroolv is a logic 0, the cru is locked to the receive reference. the rroolv bit may remain set at logic 1 for several hundred milliseconds after the removal of the power on reset as the cru pll locks to the receive reference clock.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 51 register 0x10: rsop control/interrupt enable bit type function default bit 7 r/w reserved 0 bit 6 r/w dds 0 bit 5 w foof x bit 4 r/w reserved 0 bit 3 r/w bipee 0 bit 2 r/w lose 0 bit 1 r/w lofe 0 bit 0 r/w oofe 0 oofe: the oofe bit is an interrupt enable for the out of frame alarm. when oofe is set to logic one, an interrupt is generated when the out of frame alarm changes state. lofe: the lofe bit is an interrupt enable for the loss of frame alarm. when lofe is set to logic one, an interrupt is generated when the loss of frame alarm changes state. lose: the lose bit is an interrupt enable for the loss of signal alarm. when lose is set to logic one, an interrupt is generated when the loss of signal alarm changes state. bipee: the bipee bit is an interrupt enable for the section bip-8 errors. when bipee is set to logic one, an interrupt is generated when a section bip-8 error (b1) is detected. foof: the foof bit controls the framing of the rsop. when a logic one is written to foof, the rsop is forced out of frame at the next frame boundary. the foof bit is a write only bit, register reads may yield a logic one or a logic zero. dds: the dds bit is set to logic one to disable the descrambling of the sts-3c (stm-1) stream. when dds is a logic zero, descrambling is enabled. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 52 register 0x11: rsop status/interrupt status bit type function default bit 7 unused x bit 6 r bipei x bit 5 r losi x bit 4 r lofi x bit 3 r oofi x bit 2 r losv x bit 1 r lofv x bit 0 r oofv x oofv: the oofv bit is read to determine the out of frame state of the rsop. when oofv is high, the rsop is out of frame. when oofv is low, the rsop is in-frame. lofv: the lofv bit is read to determine the loss of frame state of the rsop. when lofv is high, the rsop has declared loss of frame. losv: the losv bit is read to determine the loss of signal state of the rsop. when losv is high, the rsop has declared loss of signal. oofi: the oofi bit is the out of frame interrupt status bit. oofi is set high when a change in the out of frame state occurs. this bit is cleared when this register is read. lofi: the lofi bit is the loss of frame interrupt status bit. lofi is set high when a change in the loss of frame state occurs. this bit is cleared when this register is read. losi: the losi bit is the loss of signal interrupt status bit. losi is set high when a change in the loss of signal state occurs. this bit is cleared when this register is read. bipei: the bipei bit is the section bip-8 interrupt status bit. bipei is set high when a section layer (b1) bit error is detected. this bit is cleared when this register is read.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 53 register 0x12: rsop section bip-8 lsb bit type function default bit 7 r sbe[7] x bit 6 r sbe[6] x bit 5 r sbe[5] x bit 4 r sbe[4] x bit 3 r sbe[3] x bit 2 r sbe[2] x bit 1 r sbe[1] x bit 0 r sbe[0] x register 0x13: rsop section bip-8 msb bit type function default bit 7 r sbe[15] x bit 6 r sbe[14] x bit 5 r sbe[13] x bit 4 r sbe[12] x bit 3 r sbe[11] x bit 2 r sbe[10] x bit 1 r sbe[9] x bit 0 r sbe[8] x sbe[15:0]: bits sbe[15:0] represent the number of section bip-8 errors (b1) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rsop section bip-8 register addresses. such a write transfers the internally accumulated error count to the section bip-8 registers within approximately 7 m s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop and racp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 54 register 0x14: tsop control bit type function default bit 7 unused x bit 6 r/w d s 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w lais 0 lais: the lais bit controls the insertion of line alarm indication signal (ais). when lais is set to logic one, the tsop inserts ais into the transmit sonet stream. activation or deactivation of line ais insertion is synchronized to frame boundaries. line ais insertion results in all bits of the sonet frame being set to 1 prior to scrambling except for the section overhead. the lais bit is logically ored with the external tlais input. ds: the ds bit is set to logic one to disable the scrambling of the sts-3c or sts-1 stream. when ds is a logic zero, scrambling is enabled. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 55 register 0x15: tsop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w dlos 0 bit 1 r/w dbip8 0 bit 0 r/w dfp 0 dfp: the dfp bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the a1 section overhead framing byte. when dfp is set to logic one, the a1 bytes are set to 0x76 instead of 0xf6. dbip8: the dbip8 bit controls the insertion of bit errors continuously in the section bip-8 byte (b1). when dbip8 is set to logic one, the b1 byte is inverted. dlos: the dlos bit controls the insertion of all zeros in the transmit stream. when dlos is set to logic one, the transmit stream is forced to 0x00.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 56 register 0x18: rlop control/status bit type function default bit 7 r/w bipword 0 bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 unused x bit 1 r laisv 0 bit 0 r rdiv 0 rdiv: the rdiv bit is read to determine the remote defect indication state of the rlop. when rdiv is high, the rlop has declared line rdi. laisv: the laisv bit is read to determine the line ais state of the rlop. when laisv is high, the rlop has declared line ais. bipword: the bipword bit controls the accumulation of b2 errors. when bipword is logic one, the b2 error event counter is incremented only once per frame whenever one or more b2 bit errors occur during that frame. when bipword is logic zero, the b2 error event counter is incremented for each b2 bit error that occurs during that frame (the counter can be incremented up to 8 times per frame for sts-1 and 24 times per frame for sts-3c). reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 57 register 0x19: rlop interrupt enable/interrupt status bit type function default bit 7 r/w febee 0 bit 6 r/w bipee 0 bit 5 r/w laise 0 bit 4 r/w rdie 0 bit 3 r febei x bit 2 r bipei x bit 1 r laisi x bit 0 r rdii x rdii: the rdii bit is the far end receive failure interrupt status bit. rdii is set high when a change in the line rdi state occurs. this bit is cleared when this register is read. laisi: the laisi bit is the line ais interrupt status bit. laisi is set high when a change in the line ais state occurs. this bit is cleared when this register is read. bipei: the bipei bit is the line bip interrupt status bit. bipei is set high when a line layer (b2) bit error is detected. this bit is cleared when this register is read. febei: the febei bit is the line far end block error interrupt status bit. febei is set high when a line layer febe (z2) is detected. this bit is cleared when this register is read. rdie: the rdie bit is an interrupt enable for the far end receive failure alarm. when rdie is set to logic one, an interrupt is generated when rdi changes state. laise: the laise bit is an interrupt enable for line ais. when laise is set to logic one, an interrupt is generated when line ais changes state. bipee: the bipee bit is an interrupt enable for the line bip-24 errors. when bipee is set to logic one, an interrupt is generated when a line bip-24 error (b2) is detected.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 58 febee: the febee bit is an interrupt enable for the line far end block errors. when febe (z2) is detected.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 59 register 0x1a: rlop line bip-8/24 lsb bit type function default bit 7 r lbe[7] x bit 6 r lbe[6] x bit 5 r lbe[5] x bit 4 r lbe[4] x bit 3 r lbe[3] x bit 2 r lbe[2] x bit 1 r lbe[1] x bit 0 r lbe[0] x register 0x1b: rlop line bip-8/24 bit type function default bit 7 r lbe[15] x bit 6 r lbe[14] x bit 5 r lbe[13] x bit 4 r lbe[12] x bit 3 r lbe[11] x bit 2 r lbe[10] x bit 1 r lbe[9] x bit 0 r lbe[8] x register 0x1c: rlop line bip-8/24 msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r lbe[19] x bit 2 r lbe[18] x bit 1 r lbe[17] x bit 0 r lbe[16] x lbe[19:0] bits lbe[19:0] represent the number of line bip-8/24 errors (b2) that have been detected since the last time the error count was polled. the error count is polled by writing to any of the rlop line bip register or line febe register addresses. such a write transfers the internally accumulated error count to the line bip registers within approximately 7 m s and simultaneously resets the internal counter to begin a new cycle of error accumulation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 60 the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 61 register 0x1d: rlop line febe lsb bit type function default bit 7 r lfe[7] x bit 6 r lfe[6] x bit 5 r lfe[5] x bit 4 r lfe[4] x bit 3 r lfe[3] x bit 2 r lfe[2] x bit 1 r lfe[1] x bit 0 r lfe[0] x register 0x1e: rlop line febe bit type function default bit 7 r lfe[15] x bit 6 r lfe[14] x bit 5 r lfe[13] x bit 4 r lfe[12] x bit 3 r lfe[11] x bit 2 r lfe[10] x bit 1 r lfe[9] x bit 0 r lfe[8] x register 0x1f: rlop line febe msb bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 r lfe[19] x bit 2 r lfe[18] x bit 1 r lfe[17] x bit 0 r lfe[16] x lfe[19:0] bits lfe[19:0] represent the number of line febe errors (z2) that have been detected since the last time the error count was polled. the error count is polled by writing to any of the rlop line bip register or line febe register addresses. such a write transfers the internally accumulated error count to the line febe registers within approximately 7 m s and simultaneously resets the internal counter to begin a new cycle of error accumulation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 62 the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 63 register 0x20: tlop control bit type function default bit 7 unused x bit 6 r/w reserved 0 bit 5 r/w reserved 0 bit 4 r/w reserved 0 bit 3 r/w reserved 0 bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w rdi 0 rdi: the rdi bit controls the insertion of line far end receive failure (rdi). when rdi is set to logic one, the tlop inserts line rdi into the transmit sonet stream. line rdi is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of the k2 byte of the transmit stream. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 64 register 0x21: tlop diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 unused x bit 1 unused x bit 0 r/w dbip 0 dbip24: the dbip bit controls the insertion of bit errors continuously in the line bip byte(s) (b2). when dbip is set to logic one, the b2 byte(s) are inverted.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 65 register 0x30: rpop status/control bit type function default bit 7 r/w reserved 0 bit 6 unused x bit 5 r lop x bit 4 unused x bit 3 r pais x bit 2 r prdi x bit 1 unused x bit 0 r/w reserved 0 this register allows the status of path level alarms to be monitored. prdi, pais,lop: the prdi, pais, and lop bits reflect the current state of the corresponding path level alarms. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 66 register 0x31: rpop interrupt status bit type function default bit 7 r psli x bit 6 unused x bit 5 r lopi x bit 4 unused x bit 3 r paisi x bit 2 r prdii x bit 1 r bipei x bit 0 r febei x this register allows identification and acknowledgment of path level alarm and error event interrupts. febei, bipei: the bipei and febei bits are set to logic one when the corresponding event, a path bip-8 error or path febe is detected. prdii, paisi, lopi: the prdii, paisi, and lopi bits are set to logic one when a transition occurs in the corresponding alarm state. psli: the psli bit is set to logic one when a change is detected in the path signal label register. the current path signal label can be read from the rpop path signal label register. these bits (and the interrupt) are cleared when this register is read.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 67 register 0x33: rpop interrupt enable bit type function default bit 7 r/w psle 0 bit 6 r/w reserved 0 bit 5 r/w lope 0 bit 4 r/w reserved 0 bit 3 r/w paise 0 bit 2 r/w prdie 0 bit 1 r/w bipee 0 bit 0 r/w febee 0 this register allows interrupt generation to be enabled for path level alarm and error events. febee: when a 1 is written to the febee interrupt enable bit position, the reception of one or more febes will activate the interrupt output. bipee: when a 1 is written to the bipee interrupt enable bit position, the detection of one or more path bip-8 errors will activate the interrupt output. prdie, paise: when a 1 is written to the prdie interrupt enable bit position, a change in the path remote defect indication state will activate the interrupt output. when a 1 is written to the paise interrupt enable bit position, a change in the path ais state will activate the interrupt output. lope: when a 1 is written to the lope interrupt enable bit position, a change in the loss of pointer state will activate the interrupt output. psle: when a 1 is written to the psle interrupt enable bit position, a change in the path signal label will activate the interrupt output. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 68 register 0x37: rpop path signal label bit type function default bit 7 r psl[7] x bit 6 r psl[6] x bit 5 r psl[5] x bit 4 r psl[4] x bit 3 r psl[3] x bit 2 r psl[2] x bit 1 r psl[1] x bit 0 r psl[0] x this register allows the received path signal label byte to be read. psl[7:0]: the psl7 - psl0 bits contain the path signal label byte (c2). the value in this register is updated to a new path signal label value if the same new value is observed for three consecutive frames.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 69 register 0x38: rpop path bip-8 lsb bit type function default bit 7 r pbe[7] x bit 6 r pbe[6] x bit 5 r pbe[5] x bit 4 r pbe[4] x bit 3 r pbe[3] x bit 2 r pbe[2] x bit 1 r pbe[1] x bit 0 r pbe[0] x register 0x39: rpop path bip-8 msb bit type function default bit 7 r pbe[15] x bit 6 r pbe[14] x bit 5 r pbe[13] x bit 4 r pbe[12] x bit 3 r pbe[11] x bit 2 r pbe[10] x bit 1 r pbe[9] x bit 0 r pbe[8] x these registers allow path bip-8 errors to be accumulated. pbe[15:0]: bits pbe[15:0] represent the number of path bip-8 errors (b3) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rpop path bip-8 register addresses or to either of the rpop path febe register addresses. such a write transfers the internally accumulated error count to the path bip-8 registers within approximately 7 m s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 70 register 0x3a: rpop path febe lsb bit type function default bit 7 r pfe7 x bit 6 r pfe6 x bit 5 r pfe5 x bit 4 r pfe4 x bit 3 r pfe3 x bit 2 r pfe2 x bit 1 r pfe1 x bit 0 r pfe0 x register 0x3b: rpop path febe msb bit type function default bit 7 r pfe15 x bit 6 r pfe14 x bit 5 r pfe13 x bit 4 r pfe12 x bit 3 r pfe11 x bit 2 r pfe10 x bit 1 r pfe9 x bit 0 r pfe8 x these registers allow path febes to be accumulated. pfe[15:0]: bits pfe[15:0] represent the number of path febe errors (g1) that have been detected since the last time the error count was polled. the error count is polled by writing to either of the rpop path bip-8 register addresses or to either of the rpop path febe register addresses. such a write transfers the internally accumulated error count to the path febe registers within approximately 7 m s and simultaneously resets the internal counter to begin a new cycle of error accumulation. this transfer and reset is carried out in a manner that ensures that coincident events are not lost. the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 71 register 0x3dh: rpop path bip-8 configuration bit type function default bit 7 r/w reserved 0 bit 6 r/w reserved 0 bit 5 r/w blkbip 0 bit 4 r/w reserved 0 bit 3 unused x bit 2 r/w reserved 0 bit 1 r/w reserved 0 bit 0 r/w reserved 0 blkbip: when set high, the block bip-8 bit (blkbip) indicates that path bip-8 errors are to be reported and accumulated on a block basis. a single bip error is accumulated and reported to the return transmit path overhead processor if one or more of the bip-8 results indicates a mismatch. when blkbip is set low, bip-8 errors are accumulated and reported on a bit basis.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 72 register 0x40: tpop control/diagnostic bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r/w reserved 0 bit 1 r/w db3 0 bit 0 r/w pais 0 this register allows insertion of path level alarms and diagnostic signals. pais: the pais bit controls the insertion of sts path alarm indication signal. when a logic one is written to this bit position, the complete spe, and the pointer bytes (h1, h2, and h3) are overwritten with the all ones pattern. when a logic zero is written to this bit position, the pointer bytes and the spe are processed normally. db3: the db3 bit controls the inversion of the b3 byte value. when a logic one is written to this bit position, the b3 byte is inverted, causing the insertion of eight path bip-8 errors per frame. when a logic zero is written to this bit position, the b3 byte is transmitted uncorrupted.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 73 register 0x41: tpop pointer control bit type function default bit 7 unused x bit 6 r/w ftptr 0 bit 5 r/w sos 0 bit 4 r/w pld 0 bit 3 r/w ndf 0 bit 2 r/w nse 0 bit 1 r/w pse 0 bit 0 r/w reserved 0 this register allows control over the transmitted payload pointer for diagnostic purposes. pse: the pse bit controls the insertion of positive pointer movements. a zero to one transition on this bit enables the insertion of a single positive pointer justification in the outgoing stream. this register bit is automatically cleared when the pointer movement is inserted. this bit has no effect if the fixptr bit of the master control register is a logic 1. nse: the nse bit controls the insertion of negative pointer movements. a zero to one transition on this bit enables the insertion of a single negative pointer justification in the outgoing stream. this register bit is automatically cleared when the pointer movement is inserted. this bit has no effect if the fixptr bit of the master control register is a logic 1. ndf: the ndf bit controls the insertion of new data flags in the inserted payload pointer. when a logic one is written to this bit position, the pattern contained in the ndf[3:0] bit positions in the arbitrary pointer msb register is inserted continuously in the payload pointer. when a logic zero is written to this bit position, the normal pattern (0110) is inserted in the payload pointer. pld: the pld bit controls the loading of the pointer value contained in the arbitrary pointer registers. normally, the arbitrary pointer registers are written to set up the arbitrary new pointer value and a logic one is then written to this bit position to load the new pointer value. if a legal value (i.e. 0 pointer value 782) is transferred from the arbitrary pointer registers, the transmit payload pointer will immediately change to the
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 74 corresponding byte position. if a value greater than 782 is transferred, the payload pointer remains unchanged. this bit is automatically cleared after the new payload pointer has been loaded. this bit has no effect if the fixptr bit of the master control register is a logic 1. sos: the sos bit controls the stuff opportunity spacing between consecutive spe positive or negative stuff events. when sos is a logic zero, stuff events may be generated every frame as controlled by the pse and nse register bits described above. when sos is a logic one, stuff events may be generated at a maximum rate of once every four frames. ftptr: the force transmit pointer bit (ftptr) enables the insertion of the pointer value contained in the arbitrary pointer registers into the transmit stream for diagnostic purposes. this allows upstream payload mapping circuitry to continue functioning normally and a valid spe to continue to be generated, although it is unlikely to be extracted by far end circuitry. if ftptr is set to logic 1, the aptr[9:0] bits of the arbitrary pointer registers are inserted into the h1 and h2 bytes of the transmit stream. at least one corrupted pointer is guaranteed to be sent. if ftptr is a logic 0, a valid pointer is inserted. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 75 register 0x45: tpop arbitrary pointer lsb bit type function default bit 7 r/w aptr[7] 0 bit 6 r/w aptr[6] 0 bit 5 r/w aptr[5] 0 bit 4 r/w aptr[4] 0 bit 3 r/w aptr[3] 0 bit 2 r/w aptr[2] 0 bit 1 r/w aptr[1] 0 bit 0 r/w aptr[0] 0 this register allows an arbitrary pointer to be inserted for diagnostic purposes. aptr[7], aptr[6], aptr[5], aptr[4], aptr[3], aptr[2], aptr[1], aptr[0]: the aptr[7:0] bits, along with the aptr[9:8] bits in the arbitrary pointer msb register are used to set an arbitrary payload pointer value. the arbitrary pointer value is transferred by writing a logic one to the pld bit in the pointer control register. a legal value (i.e. 0 pointer value 782) results in the transmit payload pointer immediately changing to the corresponding byte position. if a value greater than 782 is transferred, the payload pointer remains unchanged. if the ftptr bit in the pointer control register is a logic 1, the current aptr[9:0] value is inserted into the payload pointer bytes (h1 and h2) in the transmit stream.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 76 register 0x46: tpop arbitrary pointer msb bit type function default bit 7 r/w ndf[3] 1 bit 6 r/w ndf[2] 0 bit 5 r/w ndf[1] 0 bit 4 r/w ndf[0] 1 bit 3 r/w s[1] 0 bit 2 r/w s[0] 0 bit 1 r/w aptr[9] 0 bit 0 r/w aptr[8] 0 this register allows an arbitrary pointer to be inserted for diagnostic purposes. aptr[9], aptr[8]: the aptr[9:8] bits, along with the aptr[7:0] bits in the tpop arbitrary pointer lsb register are used to set an arbitrary payload pointer value. the arbitrary pointer value is inserted in the outgoing stream by writing a logic one to the pld bit in the tpop pointer control register. s[1], s[0]: the s[1:0] bits contain the value inserted in the s[1:0] bit positions (also referred to as the unused bits) in the payload pointer. ndf[3], ndf[2], ndf[1], ndf[0]: the ndf[3:0] bits contain the value inserted in the ndf bit positions when an arbitrary new payload pointer value is inserted (using the pld bit in the pointer control register) or when new data flag generation is enabled using the ndf bit in the tpop pointer control register.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 77 register 0x48: tpop path signal label bit type function default bit 7 r/w c2[7] 0 bit 6 r/w c2[6] 0 bit 5 r/w c2[5] 0 bit 4 r/w c2[4] 1 bit 3 r/w c2[3] 0 bit 2 r/w c2[2] 0 bit 1 r/w c2[1] 1 bit 0 r/w c2[0] 1 this register allows control over the path signal label. c2[7], c2[6], c2[5], c2[4], c2[3], c2[2], c2[1], c2[0]: the c2[7:0] bits are inserted in the c2 byte position in the transmit stream.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 78 register 0x49: tpop path status bit type function default bit 7 r/w febe[3] 0 bit 6 r/w febe[2] 0 bit 5 r/w febe[1] 0 bit 4 r/w febe[0] 0 bit 3 r/w prdi 0 bit 2 r/w g1[2] 0 bit 1 r/w g1[1] 0 bit 0 r/w g1[0] 0 this register allows control over the path status byte. febe[3], febe[2], febe[1], febe[0]: the febe[3:0] bits are inserted in the febe bit positions in the path status byte. the value contained in febe[3:0] is cleared after being inserted in the path status byte. any non-zero febe[3:0] value overwrites the value that would normally have been inserted based on the number of febes accumulated during the last frame. when reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending. prdi: the prdi bit controls the insertion of the path remote defect indication (rdi). when a logic one is written to this bit position, the prdi bit position in the path status byte (g1) is set high. if the autordi bit is a logic one, an alarm state also sets the prdi bit high. when a logic zero is written to this bit position, the prdi bit position in the path status byte is set low provided autordi is low or no alarms are currently active. g1[2], g1[1], g1[0]: the g1[2:0] bits are inserted in the unused bit positions in the path status byte .
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 79 register 0x50: racp control/status bit type function default bit 7 r oocdv x bit 6 r/w rxptyp 0 bit 5 r/w pass 0 bit 4 r/w discor 0 bit 3 r/w hcspass 0 bit 2 r/w hcsadd 1 bit 1 r/w ddscr 0 bit 0 r/w fiforst 0 fiforst: the fiforst bit is used to reset the four cell receive fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and ignores writes. the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. ddscr: the ddscr bit controls the descrambling of the cell payload. when ddscr is a logic one, cell payload descrambling is disabled. when ddscr is a logic zero, payload descrambling is enabled. hcsadd: the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to comparison. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is compared. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is compared. hcspass: the hcspass bit controls the dropping of cells based on the detection of an uncorrectable hcs error. when hcspass is a logic zero, cells containing an uncorrectable hcs error are dropped. when hcspass is a logic one, cells are passed to the receive fifo regardless of errors detected in the hcs. in addition, the hcs verification finite state machine never exits the correction mode. regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'hunt' or 'presync' states. discor: the discor bit disables the hcs error correction algorithm. when discor is a logic zero, the error correction algorithm is enabled, and single bit errors detected in the cell header are corrected. when discor is a logic one, the
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 80 error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable hcs error. pass: the pass bit controls the function of the cell filter. when pass is written with a logic zero, all cells matching the cell filter are dropped. when pass is a logic one, the match header pattern registers are ignored and filtering of cells with vpi and vci fields set to 0 is not performed. the default state of this bit together with the default states of the bits in the match mask and match pattern registers enable the dropping of cells containing all zero vci and vpi fields. rxptyp: the rxptyp bit selects even or odd parity for outputs rxprty. when it is set to logic one, output rxprty is the even parity bit for outputs rdat[7:0]. when it is set to logic zero, rxprty is the odd parity bits for outputs rdat[7:0]. oocdv: the oocdv bit indicates the cell delineation state. when oocdv is set high, the cell delineation state machine is in the 'hunt' or 'presync' states, and is hunting for the cell boundaries in the synchronous payload envelope. when oocdv is set low, the cell delineation state machine is in the 'sync' state and cells are passed through the receive fifo.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 81 register 0x51: racp interrupt enable/status bit type function default bit 7 r/w oocde 0 bit 6 r/w hcse 0 bit 5 r/w fifoe 0 bit 4 r oocdi x bit 3 r chcsi x bit 2 r uhcsi x bit 1 r fovri x bit 0 unused x fovri: the fovri bit is set high when a fifo overrun occurs. this bit is reset immediately after a read to this register. uhcsi: the uhcsi bit is set high when an uncorrectable hcs error is detected. this bit is reset immediately after a read to this register. chcsi: the chcsi bit is set high when a correctable hcs error is detected. this bit is reset immediately after a read to this register. oocdi: the oocdi bit is set high when a change of cell delineation state has occurred. the oocdi bit is set high when the racp block transitions from the presync state to the sync state and from the sync state to the hunt state. this bit is reset immediately after a read to this register. fifoe: the fifoe bit enables the generation of an interrupt due to a fifo overrun error condition. when fifoe is set to logic one, the interrupt is enabled. hcse: the hcse bit enables the generation of an interrupt due to the detection of a correctable or an uncorrectable hcs error. when hcse is set to logic one, the interrupt is enabled. oocde: the oocde bit enables the generation of an interrupt due to a change of cell delineation state. when oocde is set to logic one, the interrupt is enabled.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 82 register 0x52: racp match header pattern bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[2] 0 bit 2 r/w pti[1] 0 bit 1 r/w pti[0] 0 bit 0 r/w clp 0 this register extends the cell filtering criteria beyond the all zeros pattern that must be present in the vpi and vci fields of the idle or unassigned cell. the pass bit in the racp control/status register must be set to logic zero to enable dropping of idle/unassigned cells matching the pattern defined by the contents of this register and the racp match header mask register. gfc[3:0]: the gfc[3:0] bits contain the pattern to match in the first, second, third and fourth bits of the first octet of the 53 octet cell, in conjunction with the racp match header mask register. pti[2:0]: the pti[2:0] bits contain the pattern to match in the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell, in conjunction with the racp match header mask register. clp: the clp bit contains the pattern to match in the eighth bit of the fourth octet of the 53 octet cell, in conjunction with the racp match header mask register.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 83 register 0x53: racp match header mask bit type function default bit 7 r/w mgfc[3] 0 bit 6 r/w mgfc[2] 0 bit 5 r/w mgfc[1] 0 bit 4 r/w mgfc[0] 0 bit 3 r/w mpti2] 0 bit 2 r/w mpti[1] 0 bit 1 r/w mpti[0] 0 bit 0 r/w mclp 0 the mask contained in this register is applied to the racp match header pattern register to select the bits included in the cell filter. a logic one in any bit position enables the corresponding bit in the pattern register to be compared. a logic zero causes the masking of the corresponding bit. mgfc[3:0]: the mgfc[3:0] bits contain the mask pattern for the first, second, third and fourth bits of the first octet of the 53 octet cell. mpti3:0]: the mpti[3:0] bits contain the mask pattern for the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell. mclp: the mclp bit contains the mask pattern for the eighth bit of the fourth octet of the 53 octet cell.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 84 register 0x54: racp correctable hcs error count bit type function default bit 7 r chcs[7] x bit 6 r chcs[6] x bit 5 r chcs[5] x bit 4 r chcs[4] x bit 3 r chcs[3] x bit 2 r chcs[2] x bit 1 r chcs[1] x bit 0 r chcs[0] x chcs[7:0]: the chcs[7:0] bits indicate the number of correctable hcs error events that occurred during the last accumulation interval. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the correctable hcs error count register address, or to the uncorrectable hcs error count register address. the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 85 register 0x55: racp uncorrectable hcs error count bit type function default bit 7 r uhcs[7] x bit 6 r uhcs[6] x bit 5 r uhcs[5] x bit 4 r uhcs[4] x bit 3 r uhcs[3] x bit 2 r uhcs[2] x bit 1 r uhcs[1] x bit 0 r uhcs[0] x uhcs[7:0]: the uhcs[7:0] bits indicate the number of uncorrectable hcs error events that occurred during the last accumulation interval. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the correctable hcs error count register address, or to the uncorrectable hcs error count register address. the error count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 86 register 0x56: racp receive cell counter (lsb) bit type function default bit 7 r rcell[7] x bit 6 r rcell[6] x bit 5 r rcell[5] x bit 4 r rcell[4] x bit 3 r rcell[3] x bit 2 r rcell[2] x bit 1 r rcell[1] x bit 0 r rcell[0] x register 0x57: racp receive cell counter bit type function default bit 7 r rcell[15] x bit 6 r rcell[14] x bit 5 r rcell[13] x bit 4 r rcell[12] x bit 3 r rcell[11] x bit 2 r rcell[10] x bit 1 r rcell[9] x bit 0 r rcell[8] x register 0x58: racp receive cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r rcell[18] x bit 1 r rcell[17] x bit 0 r rcell[16] x rcell[18:0]: the rcell[18:0] bits indicate the number of cells received and written into the receive fifo during the last accumulation interval. cells received and filtered due to hcs errors or idle/unassigned cell matches are not counted. the counter should be polled every second to avoid saturating. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 87 correctable hcs error count register addresses, the uncorrectable hcs error count register addresses or the receive cell counter register addresses. the cell count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 88 register 0x59: racp configuration bit type function default bit 7 r/w rgfce[3] 1 bit 6 r/w rgfce[2] 1 bit 5 r/w rgfce[1] 1 bit 4 r/w rgfce[0] 1 bit 3 r/w fsen 1 bit 2 r/w rcalevel0 1 bit 1 r/w hcsftr[1] 0 bit 0 r/w hcsftr[0] 0 the configuration register is provided at racp read/write address 9. hcsftr[1:0]: the hcs filter bits, hscftr[1:0], indicate the number of consecutive error free cells required while in detection mode before reverting back to correction mode. please refer to fig. 4 for details. hcsftr[1:0] cell acceptance threshold 00 one atm cell with correct hcs before resumption of cell acceptance. this cell is accepted. 01 two atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. 10 four atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. 11 eight atm cells with correct hcs before resumption of cell acceptance. the last cell is accepted. rcalevel0: the rca level 0 bit, rcalevel0, determines what output rca indicates when it transitions low. when rcalevel0 is set to logic one, a high to low transition on output rca indicates that the receive fifo is empty. when rcalevel0 is set to logic zero, a high to low transition on output rca indicates that the receive fifo is near empty and contains four only bytes. fsen: the active high fix stuff control enable bit fsen selects the expected payload mapping of atm cells when sts-1 mapping is selected. when fsen is set to logic one, it is assumed columns 30 and 59 of the synchronous payload
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 89 envelope (spe) contain fixed stuff bytes. when fsen is set to logic zero, it is assumed atm payload fills the entire spe except the path overhead column. rgfce[3:0]: the receive gfc enable bits, rgfce[3:0], determine which generic flow control bits are presented on the rgfc output. rgfce[3] corresponds to the most significant gfc bit (first bit in the cell). if a rgfce bit is a logic 1, the rgfc output presents in the appropriate bit location the state of the associated gfc bit in the current cell; otherwise, rfgc is deasserted low.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 90 register 0x60: tacp control/status bit type function default bit 7 r/w fifoe 0 bit 6 r tsoci x bit 5 r fovri x bit 4 r/w dhcs 0 bit 3 r/w reserved 0 bit 2 r/w hcsadd 1 bit 1 r/w dscr 0 bit 0 r/w fiforst 0 fiforst: the fiforst bit is used to reset the four cell transmit fifo. when fiforst is set to logic zero, the fifo operates normally. when fiforst is set to logic one, the fifo is immediately emptied and ignores writes. the fifo remains empty and continues to ignore writes until a logic zero is written to fiforst. dscr: the dscr bit controls the scrambling of the cell payload. when dscr is a logic one, cell payload scrambling is disabled. when dscr is a logic zero, payload scrambling is enabled. hcsadd: the hcsadd bit controls the addition of the coset polynomial, x 6 +x 4 +x 2 +1, to the hcs octet prior to insertion in the synchronous payload envelope. when hcsadd is a logic one, the polynomial is added, and the resulting hcs is inserted. when hcsadd is a logic zero, the polynomial is not added, and the unmodified hcs is inserted. reserved: the reserved bit must be programmed to logic zero for proper operation. dhcs: the dhcs bit controls the insertion of hcs errors for diagnostic purposes. when dhcs is set to logic one, the hcs octet is inverted prior to insertion in the synchronous payload envelope. fovri: the fovri bit is set high when a fifo overrun occurs. this bit is reset immediately after a read to this register tsoci: the tsoci bit is set high when the tsoc input is sampled high during any
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 91 position other than the first byte. the write address counter is reset to the first byte of the cell when tsoc is sampled high. this bit is reset immediately after a read to this register. fifoe: the fifoe bit enables the generation of an interrupt due to a fifo overrun error condition, or when the tsoc input is sampled high during any position other than the first byte. when fifoe is set to logic one, the interrupt is enabled.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 92 register 0x61: tacp idle/unassigned cell header pattern bit type function default bit 7 r/w gfc[3] 0 bit 6 r/w gfc[2] 0 bit 5 r/w gfc[1] 0 bit 4 r/w gfc[0] 0 bit 3 r/w pti[2] 0 bit 2 r/w pti[1] 0 bit 1 r/w pti[0] 0 bit 0 r/w clp 0 gfc[3:0]: the gfc[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. cell rate decoupling is accomplished by transmitting idle/unassigned cells when the tacp detects that no outstanding cells exist in the transmit fifo. the all zeros pattern is transmitted in the vci and vpi fields of the idle cell. pti[3:0]: the pti[3:0] bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the tacp detects that no outstanding cells exist in the transmit fifo. clp: the clp bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. idle cells are transmitted when the tacp detects that no outstanding cells exist in the transmit fifo.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 93 register 0x62: tacp idle/unassigned cell payload octet pattern bit type function default bit 7 r/w icp[7] 0 bit 6 r/w icp[6] 1 bit 5 r/w icp[5] 1 bit 4 r/w icp[4] 0 bit 3 r/w icp[3] 1 bit 2 r/w icp[2] 0 bit 1 r/w icp[1] 1 bit 0 r/w icp[0] 0 icp[7:0]: the icp[7:0] bits contain the pattern inserted in the payload octets of the idle or unassigned cell. cell rate decoupling is accomplished by transmitting idle/unassigned cells when the tacp detects that no outstanding cells exist in the transmit fifo. bit icp[7] corresponds to the most significant bit of the octet, the first bit transmitted.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 94 register 0x63: tacp fifo control bit type function default bit 7 r/w txptyp 0 bit 6 r/w txprtye 0 bit 5 reserved x bit 4 r txprtyi x bit 3 r/w fifodp[1] 0 bit 2 r/w fifodp[0] 0 bit 1 r/w tcalevel0 0 bit 0 reserved 0 tcalevel0: the active high tca level 0 bit, tcalevel0 determines what output tca indicates when it transitions low. when tcalevel0 is set to logic one, output tca indicates that the transmit fifo is full and can accept no more writes. when tcalevel0 is set to logic zero, output tca indicates that the transmit fifo is near full and can accept no more than four additional writes. fifodp[1:0]: the fifodp[1:0] bits determine the transmit fifo cell depth. fifo depth control may be important in systems where the cell latency through the tacp must be minimized. when the fifo is filled to the specified depth, the transmit cell available signal, tca is deasserted. tca is asserted only after a complete cell has been read out; therefore, the current cell being read is included in the count. the selectable fifo cell depths are shown below: fifodp[1] fifodp[0] fifo depth 0 0 4 cells 0 1 3 cells 1 0 2 cells 1 1 1 cell note that fifodp[1:0] only affects when tca is asserted. all four cells of the fifo may be filled before an over flow is declared. it is not recommended that the fifo depth be set to 1 cell. if a cell write is initiated only when tca is asserted, half the bandwidth is lost to idle/unassigned cells. for minimum latency and maximum throughput, set the fifo depth to 2 cells. reserved: the reserved bits must be programmed to logic zero for proper operation.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 95 txprtyi: the txprtyi bit indicates if a parity error was detected on the tdat[7:0] bus. this bit is cleared when this register is read. odd or even parity is selected using the txptyp bit. txprtye: the txprtye bit enables transmit parity interrupts. when set to logic one, parity errors on inputs tdat[7:0] are indicated by the txprtyi bit and the intb output. when set to logic zero, parity errors are indicated by the txprtyi bit but are not indicated on the intb output. txptyp: the txptyp bit selects even or odd parity for input txprty. when set to logic one input txprty is the even parity bit for inputs tdat[7:0]. when set to logic zero, inputs txprty is the odd parity bit for inputs tdat[7:0].
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 96 register 0x64: tacp transmit cell counter (lsb) bit type function default bit 7 r tcell[7] x bit 6 r tcell[6] x bit 5 r tcell[5] x bit 4 r tcell[4] x bit 3 r tcell[3] x bit 2 r tcell[2] x bit 1 r tcell[1] x bit 0 r tcell[0] x register 0x65: tacp transmit cell counter bit type function default bit 7 r tcell[15] x bit 6 r tcell[14] x bit 5 r tcell[13] x bit 4 r tcell[12] x bit 3 r tcell[11] x bit 2 r tcell[10] x bit 1 r tcell[9] x bit 0 r tcell[8] x register 0x66: tacp transmit cell counter (msb) bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 unused x bit 3 unused x bit 2 r tcell[18] x bit 1 r tcell[17] x bit 0 r tcell[16] x tcell[15:0]: the tcell[18:0] bits indicate the number of cells read from the transmit fifo and inserted into the spe during the last accumulation interval. idle/unassigned cells inserted into the spe are not counted. a write to any one of the transmit cell counter registers loads the registers with the current counter value and resets the internal 19 bit counter to 1 or 0.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 97 the counter reset value is dependent on if there was a count event during the transfer of the count to the transmit cell counter registers. the counter should be polled every second to avoid saturating. the contents of these registers are valid 200 ns after a transfer is triggered by a write to the transmit cell count register space. the cell count can also be polled by writing to the s/uni-lite master reset and identity / load meters register (0x00). writing to register address 0x00 loads all the error counter registers in the rsop, rlop, rpop, racp and tacp blocks.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 98 register 0x67: tacp configuration bit type function default bit 7 r/w tgfce[3] 0 bit 6 r/w tgfce[2] 0 bit 5 r/w tgfce[1] 0 bit 4 r/w tgfce[0] 0 bit 3 r/w fsen 1 bit 2 r/w h4insb 0 bit 1 r/w fixb yte[1] 0 bit 0 r/w fixb yte[0] 0 fixbyte[1:0]: the fixbyte[1:0] bits identify the byte pattern inserted into fixed byte columns of the synchronous payload envelope. fixbyte[1] fixbyte[0] byte 00 00h 01 55h 1 0 aah 11 ffh h4insb: the active low h4 insert enable, h4insb bit determines the contents of the h4 byte in the outgoing spe. if h4insb is set to logic one, the h4 byte is set to the value of 00 hexadecimal. if h4insb is set to logic zero, the h4 byte is set to the cell indicator offset value. fsen: the active high fix stuff control enable, fsen bit determines the payload mapping of atm cells for sts-1 mapping. when fsen is set to logic one, a fixed pattern is inserted into columns 30 and 59 of the synchronous payload envelope (spe). when fsen is set to logic zero, atm payload fills the entire spe except the path overhead column. tgfce[3:0]: the gfc enable bits, tgfce[3:0], enable the insertion of the associated gfc bit by the tgfc serial input. if mfc[3] is a logic 1, first bit of the 4 bit serial sequence is inserted into the most significant gfc bit transmitted. likewise, if mfc[0] is a logic 1, last bit of the sequence is inserted into the least significant gfc bit transmitted. if a bit is logic 0, the associated gfc bit value is derived from tdat[7:0] in the case of an assigned cell, or from the idle/unassigned cell header control register in the case of unassigned cells.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 99 test features description simultaneously asserting (low) the csb, rdb and wrb inputs causes all digital output pins and the data bus to be held in a high-impedance state. this test feature may be used for board testing. test mode registers are used to apply test vectors during production testing of the s/uni-lite. test mode registers (as opposed to normal mode registers) are selected when trs (a[7]) is high. test mode registers may also be used for board testing. when all of the tsbs within the s/uni-lite are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "test mode?" for details). test mode register memory map address register 0x00-0x7f normal mode registers 0x80 master test 0x81-0xff reserved for test notes on test mode register bits: 1. writing values into unused register bits has no effect. however, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. writable test mode register bits are not initialized upon reset unless otherwise noted.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 100 register 0x80: master test bit type function default bit 7 unused x bit 6 unused x bit 5 unused x bit 4 w pmctst x bit 3 w dbctrl x bit 2 r/w iotst 0 bit 1 w hizdata x bit 0 r/w hizio 0 this register is used to enable s/uni-lite test features. all bits, except pmctst, are reset to zero by a reset of the s/uni-lite. hizio,hizdata: the hizio and hizdata bits control the tri-state modes of the s/uni-lite . while the hizio bit is a logic one, all output pins of the s/uni-lite except the data bus are held in a high-impedance state. the microprocessor interface is still active. while the hizdata bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. iotst: the iotst bit is used to allow normal microprocessor access to the test registers and control the test mode in each tsb block in the s/uni-lite for board level testing. when iotst is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "test mode 0 details" in the "test features" section). dbctrl: the dbctrl bit is used to pass control of the data bus drivers to the csb pin. when the dbctrl bit is set to logic one, the csb pin controls the output enable for the data bus. while the dbctrl bit is set, holding the csb pin high causes the s/uni-lite to drive the data bus and holding the csb pin low tri-states the data bus. the dbctrl bit only has effect if the iotst bit is a logic one. the dbctrl bit overrides the hizdata bit. the dbctrl bit is used to measure the drive capability of the data bus driver pads. pmctst: the pmctst bit is used to configure the s/uni-lite for pmc's manufacturing tests. when pmctst is set to logic one, the s/uni-lite microprocessor port becomes the test access port used to run the pmc
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 101 "canned" manufacturing test vectors. the pmctst bit is logically "ored" with the iotst bit, and can only be cleared by setting csb to logic one. test mode 0 details in test mode?, the s/uni-lite allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. the iotst bit in the master test register should be set to logic one. to enable test mode?, the iotst bit in the master test register is set to logic one and the following addresses must be written with 00h: 91h, 95h, 99h, a1h, b1h, d1h and e1h. reading the following address locations returns the values for the indicated inputs : addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 82h tdat[7] tdat[6] tdat[5] tdat[4] tdat[3] tdat[2] tdat[1] tdat[0] 83h tbyp tgfc xoff tsoc txprty twrenb tfclk 84h rfclk rrdenb tsen rate[1] rate[0] rbyp the following inputs can not be read using the iotst feature: trclk+/-, rrclk+/-, rxd+/-, alos+/-, d[7:0], a[7:0], ale, csb, wrb, rdb and rstb. writing the following address locations forces the outputs to the value in the corresponding bit position: addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 90h ralm 2 rfp 2 92h int 1 96h tfpo d0h rsoc rca rcp rgfc rxprty int 1 d2h rdat[7] rdat[6] rdat[5] rdat[4] rdat[3] rdat[2] rdat[1] rdat[0] e0h rcp notes: 1.) bit int corresponds to output intb. intb is an open drain output and should be pulled high for proper operation. writing a logic one to the int bit allows the s/uni-lite to drive intb low. writing a logic zero to the int bit tristates the intb output. 2.) ralm and rfp must be clocked by vclk at least twice to become valid. the following outputs can not be controlled using the iotst feature: txc+/-, txd+/-, tclk, rxdo+/-, rclk, tclk, d[7:0] and tca.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 102 operation overhead byte usage under normal operating conditions, the s/uni-lite processes a subset of the complete transport overhead present in an sts-3c/stm-1 stream. the byte positions processed by the s/uni-lite are indicated in figures 8 and 9. fig. 8 sts-3c (stm-1) overhead transport overhead soh path overhead poh a1 a1 a1 a2 a2 a2 c1 c1 c1 b1 h1 h1 h1 h2 h2 h2 h3 h3 h3 b2 b2 b2 k2 z2 b3 g1 c2 h4
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 103 fig. 9 sts-1 overhead transport overhead soh path overhead poh a1 a2 c1 b1 h1 h2 h3 b2 k2 b3 g1 c2 h4 z2 a1, a2: the frame alignment bytes (a1, a2) locate the sonet frame in the data stream. the transmitter inserts these bytes in the outgoing stream. the receiver searches for the a1, a2 bit sequence in the incoming stream. a1 and a2 are not scrambled by the frame synchronous sonet scrambler. c1: the identification bytes identify the individual sts-1s in the byte interleaved sts-3c stream. the sequence 0x01, 0x02, 0x03 is inserted in the transmit direction. (only 0x01 is transmitted in sts-1 mode.) these bytes are ignored in the receive direction. c1 is not scrambled by the frame synchronous sonet scrambler. b1: the section bit interleaved parity byte provides a section error monitoring function. b1 is calculated over all bits of the previous frame after scrambling. b1 is placed in the current frame before scrambling. receive b1 errors are accumulated in an error event counter.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 104 h1, h2: the pointer value bytes locate the start of the synchronous payload envelope (spe) in the sonet/sdh frame. in the transmit direction, a fixed pointer value of 522 decimal, with a normal new data flag indication, is inserted in the first h1-h2 pair. the concatenation indication is inserted in the remaining two h1-h2 pairs in sts-3c mode. in the receive direction, the pointer is interpreted to locate the spe. the loss of pointer state is entered when a valid pointer cannot be found. path ais is detected when h1, h2 contain an all ones pattern. h3: the pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. the all zeros pattern is inserted in the transmit direction. this byte is ignored in the receive direction unless a negative stuff event is detected. b2: the line bit interleaved parity bytes provide a line error monitoring function. b2 is calculated over all bits of the line overhead, and the spe capacity of the previous frame before scrambling. b2 is placed in the current frame before scrambling. receive b2 errors are accumulated in an error event counter. k2: the k2 byte is used to identify line layer maintenance signals. in the transmit direction, line rdi is inserted by setting bits 6, 7, and 8 of the k2 byte to the pattern '110'. line ais is inserted by overwriting the line overhead (including bits 6, 7, and 8 of the k2 byte), and the spe with the all ones pattern before scrambling. in the receive direction, bits 6, 7, and 8 of the k2 byte are examined to determine the presence of the line ais, and the line rdi maintenance signals. z2: the growth byte provides a line far end block error function for remote performance monitoring. in the transmit direction, the number of b2 errors detected in the previous interval is inserted. this number has 25 legal values, namely 0 to 24 errors. in the receive direction, a legal z2 byte value is added to the line febe event counter. b3: the path bit interleaved parity byte provides a path error monitoring function. b3 is calculated over all bits of the spe capacity of the previous frame before scrambling. b3 is placed in the current frame before scrambling. receive b3 errors are accumulated in an error event counter. c2: the path signal label byte indicates the content of the spe. a hexadecimal value of 13 is transmitted, which indicates "mapping for atm."
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 105 g1: the path status byte provides a path far end block error function, and provides control over the path remote defect indication maintenance signal. in the transmit direction, path remote alarm indication (rdi) and the number of b3 errors detected in the previous interval are inserted. this number has 9 legal values, namely 0 to 8 errors. in the receive direction, a legal g1 byte value is added to the path febe event counter. in addition, the path remote defect indication is detected. h4: the cell offset indicator byte indicates the offset in bytes between itself, and the first cell boundary following the h4 byte. this byte is inserted correctly in the transmit direction, and is ignored in the receive direction. cell data structure atm cells may be passed to/from the s/uni-lite using a 9 bit data structure, consisting of a start of cell indication and an 8-bit wide word. the data structure is shown in the figure 10:
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 106 fig. 10 data structure bit 0 h1 h2 h4 bit 7 h5 payload1 word 1 word 2 word 3 word 4 word 5 word 6 payload48 word 53 h3 fifty-three 8-bit words are contained in this data structure. bit 7 of each word is the most significant bit (which corresponds to the first bit transmitted or received). the header check sequence octet (hcs) is passed through this structure. the start of cell indication input and output (tsoc and rsoc) are coincident with word 1 (containing the first cell header octet). word 5 of this structure contains the hcs octet. in the receive direction, cells containing uncorrectable header errors are dropped while the hcspass bit in the racp control/status register is set to logic zero. no header status information is passed within this data structure; error free headers, and "corrected" headers are passed while hcspass is a logic zero. error free headers, "corrected" headers, and headers containing uncorrectable errors are passed while hcspass is a logic one. in the transmit direction, the hcs bit in the tacp control register determines whether the hcs is calculated internally, or is inserted directly from word 5. loopback operation the s/uni-lite supports two loopback functions: line loopback, and diagnostic loopback. the diagnostic loopback connects the high speed transmit data and clock
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 107 to the high speed receive data and clock as shown in the partial block diagram in figure 11. the line loopback connects the high speed receive data and clock to the transmit data and clock. diagnostic loopback and line loopback are activated by bits contained in the s/uni-lite master control register.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 108 fig. 11 loopback operation high speed line loopback diagnostic loopback tx atm cell fifo rx atm cell fifo txd+ rrclk+ rxd+ ralm tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk trclk+ tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. alos+ driver data recovery clk rec. rbyp tbyp rxd- trclk- alos- rrclk- tclk tsen tgfc rcp tfpo txd- txc+ tcp rgfc txc- rxdo+ rxdo- rate0 rate1 atp2 atp1 txprty rxprty xoff lf+ lf- lfo tx atm cell fifo rx atm cell fifo txd+ rrclk+ rxd+ ralm tdat[7:0] tca tsoc rdat[7:0] rsoc d[7:0] a[7:0] ale csb rdb wrb rstb intb microprocessor i/f tx framer & overhead processor rx framer & overhead processor twrenb tfclk trclk+ tx atm cell processor rx atm cell processor rca rclk rfp rfclk rrdenb parallel to serial serial to parallel clk gen. alos+ driver data recovery clk rec. rbyp tbyp rxd- trclk- alos- rrclk- tclk tsen tgfc rcp tfpo txd- txc+ tcp rgfc txc- rxdo+ rxdo- rate0 rate1 atp2 atp1 txprty rxprty xoff lf+ lf- lfo
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 109 driving differential inputs single ended in some applications it may be more cost effective or technically desirable to drive the rrclk+/-, trclk+/- or alos+/- inputs with a single ended ttl or cmos signal. figure 12 illustrates the suggested configuration to achieve this. note that the rxd+/- inputs do not support single ended operation and must always be driven by a differential source. fig. 12 single ended driving differential inputs + - ttl or cmos signal zo=100 w r2 c1 r1 suni-lite pecl inputs typical values: r1 = 200 r2 = 100 c1 = 10nf w w the positive input should be grounded. the negative input should be a.c. coupled to an attenuated ttl or cmos signal. the peak to peak voltage should be between 800 mv and 2.5 v. the values of the components are not critical and may be modified for specific applications. a similar arrangement can be used for single ended ecl or pseudo-ecl signals. resistor r1 should be omitted. a pseudo-ecl signal may be d.c. coupled (as is required for alos) by replacing c1 with a short. this configuration logically inverts the input signal. board design recommendations the noise environment and signal integrity are often the limiting factors in system performance. therefore, the following board design guidelines must be followed in order to ensure proper operation: 1.) connect digital and analog grounds together at only one point close to the connector where ground is brought into the card.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 110 2.) provide separate +5 volt analog transmit, +5 volt analog receive, and +5 volt digital supplies, but otherwise connect the supply voltages together at one point close to the connector where +5 volts is brought to the card. 3.) ferrite beads are not advisable in digital switching circuits because inductive spiking (di/dt noise) is introduced into the power rail. simple rc filtering is probably the best approach provided care is taken to ensure the ir drop in the resistance does not lower the supply voltage below the recommended operating voltage. 4.) ferrite beads are recommended for tavd1, tavd2, ravd1 and ravd2. 5.) separate high-frequency decoupling capacitors are recommended for each analog power (tavd1, tavd2, ravd1 and ravd2) pin as close to the package pin as possible. separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent transients from coupling into the reference circuitry powered by tavd1 and ravd1. 6.) the high speed serial streams (txd+/- and rxd+/) must be routed with controlled impedance circuit board traces and must be terminated with a matched load. normal ttl-type design rules are not recommended and will reduce the performance of the device. interfacing to ecl or pecl devices although the txd+/- outputs are ttl compatible, only a few passive components are required to convert the signals to ecl (or pecl) logic levels. figure 13 illustrates the recommended configuration. the capacitors ac couple the outputs so that the ecl inputs are free to swing around the ecl bias voltage (v bb ). the combination of the 237 w and 50 w resistors divides the voltage down to a nominally 800mv swing. the 50 w resistors also terminate the signals. similarly, the rxd+/- inputs to the s/uni-lite are ac coupled as shown in figure 13. the s/uni-lite inputs are self-biasing to improve operating speed and waveform symmetry. for this reason, the dc blocking capacitors are always required, even when interfacing to pecl drivers. the only exception are the alos+/- inputs which must be dc coupled because of their low frequency content. the d.c blocking capacitors shown in figure 13 should be ceramic in type. a minumum value of 10 nf is recommended.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 111 fig. 13 interfacing s/uni-lite to ecl or pecl + zo=50 w suni-lite txd+ txd- 10nf 23 7 w 50 w zo=50 w 10nf 23 7 w 50 w v bb ecl buffer suni-lite driving ecl or pecl - + z o=50 w ecl buffer rxd+ rxd- 10nf 100 w z o=50 w 10nf 330 w suni-lite 330 w ecl or pecl driving suni-lite - v ee clock recovery figures 14a) and 14b) are abstractions of the clock recovery phase lock loop illustrating the connections to external components. figure 14a illustrates the asymmetrical loop filter application where the external passive components (r1, r2, c1, c2) are set to different values to account for the finite output impedance of the integral op-amp in the s/uni-lite. the asymmetrical loop filter circuit does not have good jitter transfer properties and is not recommended for new designs. figure 14b illustrates the unity gain buffer loop filter application where the integral op-amp output is buffered through a unity gain amplifier to minimize the effect of its finite output impedance on the transfer function of the pll. the unity gain buffer loop filter circuit exceeds sonet/sdh jitter tolerance and jitter transfer specifications and is recommended for new designs. additional analysis of jitter transfer and jitter tolerance issues for the s/uni-lite can be found in pmc's atm design notes "meeting sonet/sdh wan interface jitter transfer requirements with the s/uni-lite", pmc-950139
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 112 fig. 14a clock recovery circuit - asymmetrical loop filter (recommended for designs requiring maximum jitter tolerance) vco recovered clock phase/freq detector rrclk+/- opamp lf+ lf- r2 c20 lfo r1 c21 rxd+/- pre- filter ravd2 ravs2 on-chip off-chip ravs2 gnd different component values may be selected to optimize the loop behavior for each line rate: line rate (mbit/s) r1 ( w ) r2 ( w ) c20, c21 ( m f) 155.52 & 51.84 200 412 0.47 25.92 & 12.96 200 412 2.2 all resistors are 1% metal film (1/4 watt) resisters. unpolarized capacitors are recommended.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 113 fig. 14b clock recovery circuit - unity gain buffer loop filter (recommended for designs requiring bisdn-uni jitter transfer) vco recovered clock phase/freq detector rrclk+/- lf+ lfo rxd+/- pre- filter lf- ravd2 ravs2 r2 c2 on-chip off-chip opamp ravd2 r1 c1 re 2n3904 line rate (mbit/s) r1 ( w 1%) r2 ( w 1%) c1, c2 min ( m f) re ( w 1%) 155.52 68.1 90.9 4.7 100 51.84 68.1 90.9 15 100 the capacitors (c1, c2) determine the amount of "peaking" in the jitter transfer curve. the capacitor values can be 10%. the capacitors should be non-polarized because when the s/uni-lite is held in reset, the capacitors are reverse-biased at approximately 2.0v. also, for some process extremes, the capacitors may operate with a d.c. reverse-bias of up to 1.0v. the recommended values for the capacitors are not readily available in non- polarized versions. therefore, two polarized capacitors can be connected "back-to- back" (in series, anode-to-anode) to implement each capacitance in figure 14b. since these back-to-back capacitors will be in series, they should be of twice the value of the desired capacitance. this back-to-back configuration effectively creates a "bi-polar" capacitor.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 114 clocking options the s/uni-lite supports several clocking modes. figure 16 is an abstraction of the clocking topology. the external connections and application for each of the options (a and b) is illustrated in figure 17. fig. 16 conceptual clocking structure clock synthesizer clock recover y internal tx clock source a b rxd+/- trclk+/- internal rx clock source ? 8 tcl k rrclk+/-
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 115 fig. 17a mode a: clock synthesis 19.44 mhz input data stratum or free-run reference suni-lite rxd+/- rrclk+/- trclk+/- tclk s/uni-lite mode a is recommended for all public user network interfaces (unis) and for private unis and private network node interfaces (nnis) that are not synchronized to the recovered clock. the transmit clock in a public uni must conform to sonet network element (ne) requirements specified in bellcore gr-253-core. these requirements include jitter generation, short term clock stability, phase transients during synchronization failure, and possibly holdover. the 19.44 mhz clock source is typically a vcxo (or temperature compensated vcxo) locked to a primary reference source for public uni applications. the accuracy of this clock source should be within 20 ppm of 19.44 mhz to comply with the sonet/sdh network element free-run accuracy requirements. the transmit clock in a private uni or a private nni may be locked to an external reference or may free-run. the simplest implementation requires a free-running 19.44 mhz, 50 ppm, oscillator. mode a is selected by clearing the loopt bit of the master control register. trclk+/- is multiplied by eight to become the 155.52 mhz transmit clock. the clock synthesizer does not attenuate jitter below 500 khz, so trclk+/- must be jitter free. the source of trclk+/- may also be used as the clock recovery reference, rrclk+/-.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 116 fig. 17b mode b: loop timing stratum or free-run reference 19.44 mhz input data rxd+/- rrclk+/- trclk+/- tclk s/uni-lite mode b is recommended for private unis and private nnis that require synchronization to the recovered clock. the clock recovery unit attenuates jitter above 130 khz for sts-3c and above 40 khz for sts-1. mode b is selected by setting the loopt bit of the master control register. the trclk+/- inputs are ignored. normally, the transmit clock is locked to the receive data. in the event of a loss of signal condition, the transmit clock is synthesized from rrclk+/-.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 117 functional timing drop side receive interface fig. 18a receive fifo empty option (rcalevel0=1) rfclk rdat[7:0] w2 w1 rca rsoc rxprty w(1) w(n-1) w(n) w(n-2) xx xx xx rrdenb invalid read, no data available xx xx fig. 18b receive fifo near empty option (rcalevel0=0) rdat[7:0] w(n) w(n-2) rca rxprty w(n-3) w(n-4) w(n-5) w(1) w(n-1) rfclk rrdenb w2 w1 xx xx
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 118 the s/uni-lite indicates that a cell is available by asserting the receive cell available signal, rca. rca remains high until the internal fifo is near empty or empty. near empty implies that the atm layer device can initiate at most four additional reads. the atm layer device indicates, by asserting the rrdenb signal, that the data on the rdat[7:0] bus during the next rfclk cycle will be read from the s/uni-lite. figure 18a illustrates the receive fifo empty option. rca transitions low when the last word of the last cell is available on the rdat[7:0] bus. the rdat[7:0] bus, rxprty and rsoc are valid in cycles for which rca is high and rrdenb was low is the previous cycle. if the atm layer device requests a read while rca is deasserted, the phy layer device will ignore the additional reads. figure 18b illustrates the receive fifo near empty option. rca transitions low four words before the last word of the last cell is read from the s/uni-lite. rca remains low for a minimum of one rfclk clock cycle and then can transition high to indicate that there are additional cells available from the phy layer device. once rca is deasserted and has been sampled, the atm layer device can issue no more than four reads. if the atm layer device issues more reads than the allowable number, and rca remains deasserted throughout, the phy layer device will ignore the additional reads. fig. 19 receive gfc serial link rclk rgfce[3:0]=1010b rgfc rc p gfc[3] cell n gfc[2] cell n gfc[1] cell n rgfce[3:0]=1111b gfc[0] cell n 1-14 rclk cycles rgfc rc p gfc[3] cell n gfc[1] cell n 1-14 rclk cycles the receive gfc serial link diagram (figure?9) illustrates the operation of the receive generic flow control, rgfc, and receive gfc control pulse, rcp, outputs. the first rgfc bit position, which is coincident with the rcp being high, contains the
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 119 first gfc bit received and corresponds to the first bit of the cell. the rcp pulse width varies between 1 and 14 rclk cycles depending on the alignment of the atm cell and the sonet/sdh transport and path overheads. extraction of the gfc[3:0] bits is controlled by the four rgfc enable (rgfce[3:0]) bits in the racp configuration register. the output value in each gfc bit position can be forced low by setting the corresponding rgfce bit to zero. the serial link is inactive (forced low) if the s/uni-lite is out of cell delineation or if the current cell contains an uncorrectable header. drop side transmit interface fig. 20 transmit fifo twrenb tsoc tfclk tdat[7:0] w2 w3 w1 w1 w(n-2) w(n-3) w(n-4) w(n-1) w(n) txprty tca xx xx xx as shown in figure 20, the s/uni-lite indicates that there is space available for a full cell in its internal fifo by asserting the transmit cell available signal, tca. tca remains asserted until the transmit fifo is almost full. almost full implies that the s/uni-lite can accept at most an additional four writes after the current write. if tca is asserted and the atm layer device is ready to write a byte, it should assert twrenb low and present the byte on the tdat[7:0] bus. if the presented byte is the first byte of a cell, the atm layer device should also assert signal tsoc. at any time, if the atm layer device does not have a byte to write, it can deassert twrenb. when tca is deasserted and it has been sampled, the atm layer device can write no more than four bytes to the phy layer device. if the atm layer writes more than four bytes and tca remains deasserted throughout, the s/uni-lite will indicate an error condition and ignore additional writes until it asserts tca again.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 120 fig. 21 transmit gfc serial link tclk tcp gfc[3] gfc[2] gfc[1] gfc[0] tgfc xx figure 21 illustrates the transmit gfc serial link which provides the ability to insert flow control information downstream of the transmit fifo. the tcp output pulses high once per transmitted cell to initiate the transfer on the gfc bits. gfc[3] is the most significant bit and is transmitted first. the tacp configuration register controls the insertion of each serial bit. if the insertion is disabled, the default gfc value is inserted. for unassigned cells, the default is the contents of the tacp idle/unassigned cell header pattern register. for assigned cells, the default is the value received from tdat[7:0].
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 121 absolute maximum ratings ambient temperature under bias 0 c to +70 c storage temperature -40 c to +125 c supply voltage -0.5v to +6.0v voltage on any pin -0.5v to v dd +0.5v static discharge voltage 500 v latch-up current 100 ma dc input current 20 ma lead temperature +300 c absolute maximum junction temperature +150 c power dissipation 1 w
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 122 d.c. characteristics t a = 0 c to +70 c, v dd = 5 v 5% (typical conditions: t a = 25 c, v dd = 5 v) symbol parameter min typ max units conditions v il input low voltage (ttl only) -0.5 0.8 volts guaranteed input low voltage v pil input low voltage (alos+, alos- only) avd -1.8 avd -1.6 volts guaranteed alos+, alos- input low voltage referenced to ravd v ih input high voltage (ttl only) 2.0 v dd +0.5 volts guaranteed input high voltage v pih input high voltage (alos+, alos- only) avd -1.0 avd -0.8 volts guaranteed alos+, alos- input high voltage referenced to ravd v piswing input swing (rrclk+, rrclk-, rxd+, rxd-, trclk+, trclk- only) 0.6 1.0 volts input swing assuming ecl/pecl signal ac coupled as illustrated in figure 13 v ol output or bidirectional low voltage (ttl only) 0.1 0.4 volts v dd = min, i ol = -8 ma for rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk, and rclk, and 4 ma for all others, note 3 v oh output or bidirectional high voltage (ttl only) 2.4 4.7 volts v dd = min, i oh = 8 ma for rdat[7:0], rxprty, rcp, rgfc, rsoc, rca, tca, tcp, tclk, and rclk, and 4 ma for all others, note 3
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 123 v txol output or bidirectional low voltage (txd+, txd-, txc+, txc- only) 0.4 volts v dd = min, i ol = -6 ma for txd+, txd-, txc+, and txc-, note 5 v txoh output or bidirectional high voltage (txd+, txd-, txc+, txc- only) 3.9 volts v dd = min, i oh = 6 ma for txd+, txd-, txc+, and txc-, note 5 v t+ reset input high voltage 3.5 volts v t- reset input low voltage 1.0 volts v th reset input hysteresis voltage 1.0 volts i ilpu input low current +20 +83 +200 m av il = gnd, notes 1, 3 i ihpu input high current -10 +10 m av ih = v dd , notes 1, 3 i ilpd input low current -10 +10 m av il = gnd, notes 4, 3 i ihpd input high current -200 -83 -20 m av ih = v dd , notes 4, 3 i il input low current -10 +10 m av il = gnd, notes 2, 3 i ih input high current -10 +10 m av ih = v dd , notes 2, 3 c in input capacitance 5 pf excluding package, package typically 2 pf c out output capacitance 5 pf excluding package, package typically 2 pf c io bidirectional capacitance 5 pf excluding package, package typically 2 pf
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 124 i ddop operating current processing cells 156 85 185 110 ma ma v dd = 5.25 v, outputs unloaded, txd+/- = rxd+/- =155.52 mbit/s, txd+/- = rxd+/- =51.84 mbit/s, notes on d.c. characteristics: 1. input pin or bidirectional pin with internal pull-up resistor. 2. input pin or bidirectional pin without internal pull-up resistor 3. negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. input pin or bidirectional pin with internal pull-down resistor. 5. the values for v txol and v txoh ensure a minimum 600 mv swing at the ecl buffer input when the circuit shown in figure 13 is used to attenuate txd+, txd-, txc+, and txc-. 6. typical values are not production tested.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 125 microprocessor interface timing characteristics (t a = 0 c to +70 c, v dd = 5 v 5%) microprocessor interface read access (fig. 22) symbol parameter min max units ts ar address to valid read set-up time 25 ns th ar address to valid read hold time 5 ns ts alr address to latch set-up time 20 ns th alr address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lr latch to read set-up 0 ns th lr latch to read hold 5 ns tp rd valid read to valid data propagation delay 80 ns tz rd valid read negated to output tri-state 20 ns tz inth valid read negated to output tri-state 50 ns
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 126 fig. 22 microprocessor interface read timing intb tz inth (csb+rdb) valid data d[7:0] tp rd tz rd ts ar th ar valid address a[7:0] al e ts alr tv l ts lr th alr th lr notes on microprocessor interface read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor interface data bus, (d[7:0]). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. microprocessor interface timing applies to normal mode register accesses only. 5. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alr , th alr , tv l , and ts lr are not applicable.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 127 6. parameters th ar and ts ar are not applicable if address latching is used. 7. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 8. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. microprocessor interface write access (fig. 23) symbol parameter min max units ts aw address to valid write set-up time 25 ns ts dw data to valid write set-up time 20 ns ts alw address to latch set-up time 20 ns th alw address to latch hold time 10 ns tv l valid latch pulse width 20 ns ts lw latch to write set-up 0 ns th lw latch to write hold 5 ns th dw data to valid write hold time 5 ns th aw address to valid write hold time 5 ns tv wr valid write pulse width 40 ns
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 128 fig. 23 microprocessor interface write timing th dw valid data d[7:0 ] tv wr ts aw th aw ts dw (csb+wrb) a[7:0 ] valid address al e tv l ts alw ts lw th alw th lw notes on microprocessor interface write timing: 1 a valid write cycle is defined as a logical or of the csb and the wrb signals. 2. microprocessor interface timing applies to normal mode register accesses only. 3. in non-multiplexed address/data bus architectures, ale should be held high, parameters ts alw , th alw , tv l , and ts lw are not applicable. 4. parameters th aw and ts aw are not applicable if address latching is used. 5. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 6. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 129 s/uni-lite timing characteristics (t a = 0 c to +70 c, v dd = 5 v 5%) line side receive interface symbol description min max units rrclk+/rrclk- duty cycle 19.44 or 6.48 mhz 30 70 % rrclk+/rrclk- frequency tolerance ? -20 +20 ppm ? the specification may be relaxed to +/- 50 ppm if the s/uni-lite is not loop timed, or for lan applications that do not require this timing accuracy. if loop timing is enabled, the specified tolerance is required to meet the sonet free run accuracy specification under loss of signal conditions. receive alarm output (fig. 24) symbol description min max units t p ralm rclk high to ralm valid 2 20 ns t p rfp rclk high to rfp valid 2 20 ns fig. 24 receive alarm output timing tp ralm ralm rcl k tp rfp rfp
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 130 line side transmit interface (fig. 25) symbol description min max units trclk+/trclk- duty cycle 19.44 or 6.48 mhz (tbyp low) 30 70 % trclk+/trclk- frequency tolerance ? -20 +20 ppm t p tfpo tclk high to tfpo valid 3 20 ns tp txddiff txc+/txc- low to txd+/txd- valid -2 2 ns tp txdneg txc+ low to txd+ valid -3 2 ns tp txdpos txc- high to txd+ valid -2 3 ns ? the specification may be relaxed to +/- 50 ppm for lan applications that do not require this timing accuracy. the specified tolerance is required to meet the sonet free run accuracy specification.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 131 fig. 25 line side transmit interface timing tclk tp tfpo tfpo txc+ txc- tp txddiff txd+ txd- txc+ tp txdneg txd+ txc- tp txdpos txd+ drop side receive synchronous interface (fig. 26) symbol description min max units rfclk frequency 33 mhz rfclk duty cycle 40 60 % t s rrdenb rrdenb to rfclk high setup 10 ns t h rrdenb rfclk high to rrdenb hold 1 ns t p rdat rfclk high to rdat[7:0] valid 2 20 ns t p rxp rfclk high to rxprty valid 2 20 ns t p rca rfclk high to rca valid 2 20 ns t p rsoc rfclk high to rsoc valid 2 20 ns
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 132 fig. 26 drop side receive synchronous interface timing (tsen = 0) tp rxp rxprty tp rdat rdat[7:0 ] rfcl k tp rca rca tp rsoc rsoc rrdenb th rrdenb ts rrdenb
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 133 drop side receive synchronous interface (fig. 27) symbol description min max units rfclk frequency 33 mhz rfclk duty cycle 40 60 % t s rrdenb rrdenb to rfclk high setup 10 ns t h rrdenb rfclk high to rrdenb hold 1 ns t p rdat rfclk high to rdat[7:0] valid 2 20 ns t z rdat rfclk high to rdat[7:0] tristate 2 20 ns t p rxp rfclk high to rxprty valid 2 20 ns t z rxp rfclk high to rxprty tristate 2 20 ns t p rca rfclk high to rca valid 2 20 ns t p rsoc rfclk high to rsoc valid 2 20 ns t z rsoc rfclk high to rsoc tristate 2 20 ns
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 134 fig. 27 drop side receive synchronous interface timing (tsen = 1) tp rxp rxprty tz rxp tp rdat rdat[7:0 ] rfcl k tp rca rca tp rsoc rsoc rrdenb th rrdenb ts rrdenb tz rdat tz rsoc
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 135 gfc extract port (fig. 28) symbol description min max units t p rgfc rclk high to rgfc valid -1 10 ns t p rcp rclk high to rcp valid -1 10 ns fig. 28 gfc extract port timing tp rgfc rgfc rcl k tp rcp rc p drop side transmit synchronous interface (fig. 29) symbol description min max units tfclk frequency 33 mhz tfclk duty cycle 40 60 % ts twrenb twrenb set-up time to tfclk 10 ns th twrenb twrenb hold time to tfclk 1 ns t s tdat tdat[7:0] set-up time to tfclk 10 ns t h tdat tdat[7:0] hold time to tfclk 1 ns t s txp txprty set-up time to tfclk 10 ns t h txp txprty hold time to tfclk 1 ns t s tsoc tsoc set-up time to tfclk 10 ns t h tsoc tsoc hold time to tfclk 1 ns t p tca tfclk to tca valid 2 20 ns
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 136 fig. 29 drop side transmit synchronous interface ts txp th txp txprt y ts twrenb th twrenb twrenb ts tdat th tdat tdat[7:0] ts tsoc th tsoc tsoc tca tp tca tfclk
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 137 gfc insert port (fig. 30) symbol description min max units t s tgfc tgfc set-up time to tclk 10 ns t h tgfc tgfc hold time to tclk 1 ns t p tcp tclk high to tcp valid -1 10 ns fig. 30 gfc insert port timing th tgfc tgfc tclk tp tcp tcp ts tgfc notes on input timing: 1. when a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 volt point of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt point of the output. 2. all output propagation delays are measured with a 50 pf load on the outputs. 3. differential output propagation delay time is the time in nanoseconds from the crossing point of the reference signal to the crossing point of the output.
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 138 ordering and thermal information part no. description PM5346-RC 128 pin copper leadframe plastic quad flat pack (pqfp) part no. ambient temperature theta ja theta jc PM5346-RC 0 c to 70 c 60 c/w 25 c/w
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 139 mechanical information 128 pin copper leadframe rectangular plastic quad flat pack (r suffix): e 1 d e1 d1 e 128 8-12 deg a 8-12 deg a2 pin 1 designator nom. min. max. dim. aa1 a2 d d1 e e1 l e b ccc package type: body size: 14.10 14.00 13.90 0.73 0.88 1.03 0.10 14 x 20 x 2.7 mm 2.82 3.40 0.25 0.53 2.57 2.70 2.87 22.95 23.20 23.45 19.90 20.00 20.10 16.95 17.20 17.45 0.50 0.17 0.22 0.27 see detail a 128 pin metric rectangular plastic quad flatpack-mqfp gage plane, 0.25 above seating plane. detail a 0-7 deg plane seating 0.13-0.23 c l .25 a 0-10 deg. ccc c lead coplanarity notes: 1) all dimensions in millimeter. b standoff a1 3) foot length "l" is measured at c with tolerances as indicated. 2) dimensions shown are nominal
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 140 n o t e s
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ 141 n o t e s
s tandard p roduct pmc-sierra, inc. pm5346 s/uni-lite i ssue 6 saturn user network i nterface ______________________________________________________________________________________________ ______________________________________________________________________________________________ pmc-sierra, inc. 8501 commerce court burnaby, bc canada v5a 4n3 604 668 7300 n o t e s ______________________________________________________________________________________________ seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. there are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights, or conformance with sample. seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. in no event will seller be liable to buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if seller has knowledge of the possibility of such potential loss or damage and even if caused by seller? negligence. ?1996 pmc-sierra, inc. pmc-931110(r6) ref 931109(r8) issue date: march, 1996.

▲Up To Search▲

Price & Availability of PM5346-RC

	To Download PM5346-RC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .